Phytec phyCORE-LPC2292/94, Hardware Manual

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Memory Models
©
PHYTEC Messtechnik GmbH 2006 L-658e_5
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Example b)
Module Configuration:
•
Flash access time = 90 ns
•
SRAM access time = 70 ns
•
Ethernet access time = 25 ns
BCFG0 Register Configuration Value:
0x02000 28A3
IDCY : 3 -> 4 idle cycle
WST1 : 5 -> 8 CCLK cycles
RBLE : 0 -> 0 non byte partitioned device
WST2 : 5 -> 8 CCLK cycles
BUSERR : 0 -> not relevant
WPERR : 0 -> no write protection error
WP : 0 -> bank not write protected
BM : 0 -> no burst ROM bank
MW : 2 -> 32-bit wide bus
AT : 0 -> always write 0 to this field
BCFG1 Register Configuration Value:
0x02000 2483
IDCY : 3 -> 4 idle cycle
WST1 : 4 -> 7 CCLK cycles
RBLE : 1 -> byte partitioned device
WST2 : 4 -> 7 CCLK cycles
BUSERR : 0 -> not relevant
WPERR : 0 -> no write protection error
WP : 0 -> bank not write protected
BM : 0 -> no burst ROM bank
MW : 2 -> 32-bit wide bus
AT : 0 -> always write 0 to this field