Phytec phyCORE-LPC2292/94, Hardware Manual

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Contents
©
PHYTEC Messtechnik GmbH 2006 L-658e_5
Preface........................................................................................................... 1
1 Introduction......................................................................................... 3
1.1 Block Diagram ............................................................................. 6
1.2 View of the phyCORE-LPC2292/94 ........................................... 7
2 Pin Description .................................................................................... 9
3 Jumpers.............................................................................................. 17
3.1 J200, J202 Second Serial Interface ........................................... 24
3.2 J201, J203 First Serial Interface................................................ 25
3.3 J204 A/D Converter .................................................................. 26
3.4 J205, J206 Chip Select Configuration....................................... 26
3.5 J207 MCKO Signal ................................................................... 27
3.6 J208, J209 Flash Size Configuration......................................... 28
3.7 J210, J211 RAM Size Configuration ........................................ 29
3.8 J300 Flash Ready/Busy Configuration ..................................... 30
3.9 J301, J302 Flash Write Protection Configuration..................... 31
3.10 J400, J401 SRAM Configuration.............................................. 32
3.11 J402 SRAM Supply Voltage..................................................... 32
3.12 J500 through J509 Ethernet Controller SMSC
LAN91C111Configuration ........................................................ 33
3.13 J600, J601, J616 CAN Transceiver Configuration ................... 36
3.14 J602, J603, J604, J605 CAN Interfaces .................................... 37
3.15 J606 Write Protection of SPI EEPROM ................................... 38
3.16 J607 Watchdog Configuration .................................................. 39
3.17 J608, J609, J610 I
2
C Interface................................................... 40
3.18 J611, J612, J613, J614 SPI0 Interface ...................................... 40
3.19 J615 CAN Bus Level Configuration ......................................... 41
3.20 J616, J617 CAN Transceiver VCC, Pin 5................................. 42
3.21 J618 VDD_V3V3 Supply Control ............................................ 43
3.22 J619, J620 SPI Master/Slave Selection ..................................... 43
3.23 J621 WDI Signal Source ........................................................... 44
3.24 J622 RESET Signal Source....................................................... 44
3.25 J800, J801 ETM/OCDS Connector Configuration
(Only with debugCORE-LPC2292/94)...................................... 45
3.26 C210 CLKIN Configuration ...................................................... 46
4 System Configuration ....................................................................... 47
4.1 System Startup Configuration .................................................... 47
4.2 Starting the LPC2292/94 ISP Mode........................................... 48
5 Memory Models................................................................................. 49