NXP Semiconductors LPC1102 User Manual Download

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UM10429

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User manual

Rev. 1 — 20 October 2010

247 of 258

NXP Semiconductors

UM10429

Chapter 20: LPC1102 Supplementary information

Table 54. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2,

address 0x4004 4080) bit description . . . . . . .58

Table 55. IOCON_SWDIO_PIO1_3 register

(IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 56. IOCON_PIO1_6 register (IOCON_PIO1_6,

address 0x4004 40A4) bit description . . . . . . .59

Table 57. IOCON_PIO1_7 register (IOCON_PIO1_7,

address 0x4004 40A8) bit description . . . . . . .59

Table 58.  Pin description table  . . . . . . . . . . . . . . . . . . . .61
Table 59.  GPIO configuration . . . . . . . . . . . . . . . . . . . . . .63
Table 60.  Register overview: GPIO (base address port 0:

0x5000 0000; port 1: 0x5001 0000) . . . . . . . . .63

Table 61. GPIOnDATA register (GPIO0DATA, address

0x5000 0000 to 0x5000 3FFC; GPIO1DATA,
address 0x5001 0000 to 0x5001 3FFC;
GPIO2DATA, address 0x5002 0000 to 0x5002
3FFC; GPIO3DATA, address 0x5003 0000 to
0x5003 3FFC) bit description . . . . . . . . . . . . .64

Table 62. GPIOnDIR register (GPIO0DIR, address 0x5000

8000 to GPIO3DIR, address 0x5003 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 63. GPIOnIS register (GPIO0IS, address 0x5000

8004 to GPIO3IS, address 0x5003 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 64. GPIOnIBE register (GPIO0IBE, address 0x5000

8008 to GPIO3IBE, address 0x5003 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 65. GPIOnIEV register (GPIO0IEV, address 0x5000

800C to GPIO3IEV, address 0x5003 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 66. GPIOnIE register (GPIO0IE, address 0x5000

8010 to GPIO3IE, address 0x5003 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 67. GPIOnIRS register (GPIO0IRS, address 0x5000

8014 to GPIO3IRS, address 0x5003 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 68. GPIOnMIS register (GPIO0MIS, address 0x5000

8018 to GPIO3MIS, address 0x5003 8018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 69. GPIOnIC register (GPIO0IC, address 0x5000

801C to GPIO3IC, address 0x5003 801C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 70. UART pin description . . . . . . . . . . . . . . . . . . . .69
Table 71. Register overview: UART (base address: 0x4000

8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 72. UART Receiver Buffer Register (U0RBR -

address 0x4000 8000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . . .71

Table 73. UART Transmitter Holding Register (U0THR -

address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . .71

Table 74. UART Divisor Latch LSB Register (U0DLL -

address 0x4000 8000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 75. UART Divisor Latch MSB Register (U0DLM -

address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 76. UART Interrupt Enable Register (U0IER - address

0x4000 8004 when DLAB = 0) bit description 72

Table 77. UART Interrupt Identification Register (U0IIR -

address 0x4004 8008, Read Only) bit description
73

Table 78. UART Interrupt Handling . . . . . . . . . . . . . . . . . 74
Table 79. UART FIFO Control Register (U0FCR - address

0x4000 8008, Write Only) bit description . . . . . 76

Table 80. UART Line Control Register (U0LCR - address

0x4000 800C) bit description . . . . . . . . . . . . . 76

Table 81. UART Line Status Register (U0LSR - address

0x4000 8014, Read Only) bit description . . . . 77

Table 82. UART Scratch Pad Register (U0SCR - address

0x4000 8014) bit description . . . . . . . . . . . . . . 79

Table 83. Auto-baud Control Register (U0ACR - address

0x4000 8020) bit description . . . . . . . . . . . . . . 79

Table 84. UART Fractional Divider Register (U0FDR -

address 0x4000 8028) bit description . . . . . . . 83

Table 85. Fractional Divider setting look-up table . . . . . . 85
Table 86. UART Transmit Enable Register (U0TER -

address 0x4000 8030) bit description . . . . . . . 86

Table 87. UART RS485 Control register (U0RS485CTRL -

address 0x4000 804C) bit description . . . . . . 86

Table 88. UART RS-485 Address Match register

(U0RS485ADRMATCH - address 0x4000 8050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 89. SPI pin descriptions . . . . . . . . . . . . . . . . . . . . . 91
Table 90. Register overview: SPI0 (base address 0x4004

0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 91: SPI/SSP Control Register 0 (SSP0CR0 - address

0x4004 0000) bit description . . . . . . . . . . . . . . 92

Table 92: SPI/SSP Control Register 1 (SSP0CR1 - address

0x4004 0004) bit description . . . . . . . . . . . . . . 93

Table 93: SPI/SSP Data Register (SSP0DR - address

0x4004 0008) bit description . . . . . . . . . . . . . . 94

Table 94: SPI/SSP Status Register (SSP0SR - address

0x4004 000C) bit description . . . . . . . . . . . . . . 94

Table 95: SPI/SSP Clock Prescale Register (SSP0CPSR -

address 0x4004 0010) bit description . . . . . . . 95

Table 96: SPI/SSP Interrupt Mask Set/Clear register

(SSP0IMSC - address 0x4004 0014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 97: SPI/SSP Raw Interrupt Status register (SSP0RIS

- address 0x4004 0018) bit description . . . . . . 96

Table 98: SPI/SSP Masked Interrupt Status register

(SSP0MIS - address 0x4004 001C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 99: SPI/SSP interrupt Clear Register (SSP0ICR -

address 0x4004 0020) bit description . . . . . . . 97

Table 100. Counter/timer pin description . . . . . . . . . . . . 106
Table 101. Register overview: 16-bit counter/timer 0 CT16B0

(base address 0x4000 C000) . . . . . . . . . . . . 106

Table 102. Register overview: 16-bit counter/timer 1 CT16B1

(base address 0x4001 0000) . . . . . . . . . . . . 107

Table 103. Interrupt Register (TMR16B0IR - address

0x4000 C000 and TMR16B1IR - address
0x4001 0000) bit description . . . . . . . . . . . . . 108

Table 104. Timer Control Register (TMR16B0TCR - address

Summary of Contents for LPC1102

Page 1: ...UM10429 LPC1102 User manual Rev 1 20 October 2010 User manual Document information Info Content Keywords ARM Cortex M0 LPC1102 LPC1102UK Abstract LPC1102 User manual...

Page 2: ...reserved User manual Rev 1 20 October 2010 2 of 258 Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NX...

Page 3: ...purpose counter timers a 10 bit ADC and 11 general purpose I O pins 1 2 Features System ARM Cortex M0 processor running at frequencies of up to 50 MHz ARM Cortex M0 built in Nested Vectored Interrupt...

Page 4: ...ct the external clock IRC clock CPU clock and the Watchdog clock Power control Integrated PMU Power Management Unit to minimize power consumption during Sleep and Deep sleep modes Power profiles resid...

Page 5: ...TEX M0 TEST DEBUG INTERFACE FLASH 32 kB HIGH SPEED GPIO AHB TO APB BRIDGE CLOCK GENERATION POWER CONTROL SYSTEM FUNCTIONS XTALIN RESET clocks and controls SWD LPC1102 002aaf524 slave slave slave slave...

Page 6: ...ortex M0 processor The ARM Cortex M0 processor is described in detail in Section 19 2 About the Cortex M0 processor and core peripherals For the LPC1102 the ARM Cortex M0 processor core is configured...

Page 7: ...he only AHB peripherals The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying th...

Page 8: ...0x4005 8000 0x4005 C000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 0x4000 0000 WDT 32 bit counter timer 0 32 bit counter timer 1 ADC UART PMU reserved 13 10 reserved reserved reserved 21 19 reser...

Page 9: ...ee independent oscillators These are the system oscillator the Internal RC oscillator IRC and the watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular...

Page 10: ...t SYSPLLCLKSEL system PLL clock select SYSTEM CLOCK DIVIDER AHB clock 0 system AHBCLKCTRL 1 18 SPI0 PERIPHERAL CLOCK DIVIDER SPI0_PCLK UART PERIPHERAL CLOCK DIVIDER UART_PCLK WDT CLOCK DIVIDER WDT_PCL...

Page 11: ...Reserved WDTCLKSEL R W 0x0D0 WDT clock source select 0x000 Table 22 WDTCLKUEN R W 0x0D4 WDT clock source update enable 0x000 Table 23 WDTCLKDIV R W 0x0D8 WDT clock divider 0x000 Table 24 0x0DC Reserve...

Page 12: ...ion register 0x0000 EDF0 Table 35 0x23C 0x3F0 Reserved DEVICE_ID R 0x3F4 Device ID part dependent Table 36 Table 5 Register overview system control block base address 0x4004 8000 continued Name Access...

Page 13: ...em oscillator control register This register configures the frequency range for the system oscillator Table 8 System PLL control register SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Valu...

Page 14: ...as wdt_osc_clk Fclkana 2 1 DIVSEL 7 8 kHz to 1 7 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillator is...

Page 15: ...Select watchdog oscillator analog output frequency Fclkana 0x00 0x1 0 5 MHz 0x2 0 8 MHz 0x3 1 1 MHz 0x4 1 4 MHz 0x5 1 6 MHz 0x6 1 8 MHz 0x7 2 0 MHz 0x8 2 2 MHz 0x9 2 4 MHz 0xA 2 6 MHz 0xB 2 7 MHz 0xC...

Page 16: ...When using the C_CAN controller with baudrates above 100 kbit s the system oscillator must be selected Table 13 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol V...

Page 17: ...from LOW to HIGH for the update to take effect Remark When switching clock sources both clocks must be running before the clock source is updated Remark When using the C_CAN controller with baudrates...

Page 18: ...block and the PMU This clock cannot be disabled Table 17 Main clock source update enable register MAINCLKUEN address 0x4004 8074 bit description Bit Symbol Value Description Reset value 0 ENA Enable...

Page 19: ...Disable 1 Enable 8 CT16B1 Enables clock for 16 bit counter timer 1 0 0 Disable 1 Enable 9 CT32B0 Enables clock for 32 bit counter timer 0 0 0 Disable 1 Enable 10 CT32B1 Enables clock for 32 bit count...

Page 20: ...he watchdog timer The WDTCLKUEN register see Section 3 5 18 must be toggled from LOW to HIGH for the update to take effect Remark When switching clock sources both clocks must be running before the cl...

Page 21: ...20 POR captured PIO status register 0 The PIOPORCAP0 register captures the state HIGH or LOW of the PIO pins of ports 0 1 and 2 pins PIO2_0 to PIO2_7 at power on reset Each bit represents the reset st...

Page 22: ...n dependent 15 CAPPIO1_3 Raw reset status input PIO1_3 User implementation dependent 17 16 Reserved 18 CAPPIO1_6 Raw reset status input PIO1_6 User implementation dependent 19 CAPPIO1_7 Raw reset stat...

Page 23: ...nterrupt 1 etc see Table 44 up to a total of 13 interrupts Remark Each interrupt connected to a start logic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip f...

Page 24: ...ng edge 31 13 Reserved 0x0 Table 28 Start logic edge control register 0 STARTAPRP0 address 0x4004 8200 bit description continued Bit Symbol Value Description Reset value Table 29 Start logic signal en...

Page 25: ...whether or not a wake up signal has been received for a given pin Table 30 Start logic reset register 0 STARTRSRP0CLR address 0x4004 8208 bit description Bit Symbol Value Description Reset value 0 RSR...

Page 26: ...watchdog oscillator can be left running in Deep sleep mode to provide a clock for the watchdog timer or a general purpose timer if they are needed for timing a wake up event see Section 3 9 3 for det...

Page 27: ...ry are powered and running and the BOD circuit is enabled when the chip wakes up from Deep sleep mode Remark Reserved bits must be always written as indicated Table 33 Deep sleep configuration registe...

Page 28: ...re powered and running and the BOD circuit is enabled Remark Reserved bits must be always written as indicated 2 FLASH_PD Flash wake up configuration 0 0 Powered 1 Powered down 3 BOD_PD BOD wake up co...

Page 29: ...wn 0 0 Powered 1 Powered down 2 FLASH_PD Flash power down 0 0 Powered 1 Powered down 3 BOD_PD BOD power down 0 0 Powered 1 Powered down 4 ADC_PD ADC power down 1 0 Powered 1 Powered down 5 SYSOSC_PD S...

Page 30: ...address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values 3 7 Brown out detect...

Page 31: ...er registers 3 8 2 Sleep mode In Sleep mode the system clock to the ARM Cortex M0 core is stopped and execution of instructions is suspended until either a reset or an enabled interrupt occurs Periphe...

Page 32: ...ration setting in the PDSLEEPCFG Table 33 register The only clock source available in Deep sleep mode is the watchdog oscillator The watchdog oscillator can be left running in Deep sleep mode if requi...

Page 33: ...er must be enabled in the SYSAHBCLKCTRL register and the watchdog oscillator must be running in Deep sleep mode for details see Section 3 9 3 Reset from the BOD circuit In this case the BOD circuit mu...

Page 34: ...nfigured accordingly in the start logic edge control register see Table 28 The following steps must be performed to configure the counter timer and create a timed Deep sleep self wake up event 1 Confi...

Page 35: ...lues for P and M must be selected so that the PLL output clock frequency FCLKOUT is lower than 100 MHz 3 10 1 Lock detector The lock detector measures the phase difference between the rising edges of...

Page 36: ...g the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way to synchronize the change of the MSEL and PSEL values with the dividers the risk exists t...

Page 37: ...equency detector will be stopped and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is term...

Page 38: ...lue Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the number of system clocks used for flash access 10 0x0 1 system clock flash access time for system clock freq...

Page 39: ...ccess Address offset Description Reset value PCON R W 0x000 Power control register 0x0 Table 41 Power control register PCON address 0x4003 8000 bit description Bit Symbol Value Description Reset value...

Page 40: ...mand 4 result 2 5 4 Clocking routine 5 4 1 set_pll This routine sets up the system PLL according to the calling arguments If the expected clock can be obtained by simply dividing the system PLL input...

Page 41: ...n the expected system clock and the system PLL input frequency is an integer value but it can also find solutions in other cases The system PLL input frequency Param0 must be between 10000 to 25000 kH...

Page 42: ...t before it returns PLL_NOT_LOCKED In this case the PLL settings are unchanged and Param0 is returned as Result1 Hint setting Param3 equal to the system PLL frequency Hz divided by 10000 will provide...

Page 43: ..._LTE command 3 0 rom pWRD set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 25 MHz and no locking timeout set_pll returns PLL_CMD_SUCCESS in resul...

Page 44: ...r 5 LPC1102 Power profiles 5 5 Power routine 5 5 1 set_power This routine configures the device s internal power control settings according to the calling arguments The goal is to reduce active power...

Page 45: ...k new_clock False True End wait 50 s using power profiles and changing system clock use either clocking routine call or custom code to change system clock from current_clock to new_clock use either cl...

Page 46: ...egal selection is provided set_power returns PWR_INVALID_MODE and does not change the power control system PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state PWR_CPU_P...

Page 47: ...bove setup would be used in a system running at 12 MHz attempting to switch to 55 MHz system clock with a need for maximum CPU processing power Since the specified 55 MHz clock is above the 50 MHz max...

Page 48: ...ources Table 44 lists the interrupt sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more t...

Page 49: ...IFO half full Rx Timeout Rx Overrun 21 UART Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out ABTO...

Page 50: ...istics of the pads The following features are programmable pin function internal pull up pull down resistor or bus keeper function hysteresis analog input or digital mode for pads hosting the ADC inpu...

Page 51: ...istors for each pin or select the repeater mode The possible on chip resistor configurations are pull up enabled pull down enabled or no pull up pull down The default value is pull up enabled The repe...

Page 52: ...effect 7 4 Register description The I O configuration registers control the PIO port pins the inputs and outputs of all peripherals and functional blocks and the ADC input pins Each port pin PIOn_m ha...

Page 53: ...n Reset value Reference Table 46 I O configuration registers ordered by port number Port pin Register name Reference PIO0_0 IOCON_RESET_PIO0_0 Table 47 PIO0_8 IOCON_PIO0_8 Table 48 PIO0_9 IOCON_PIO0_9...

Page 54: ...tor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 7 6 Reserved 11 31...

Page 55: ...nction CT16B0_MAT2 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor e...

Page 56: ...IO1_0 address 0x4004 4078 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 000 0x0 Selects function R This function is reserved Sel...

Page 57: ...ion Values 0x4 to 0x7 are reserved 000 0x0 Selects function R This function is reserved Select one of the alternate functions below 0x1 Selects function PIO1_1 0x2 Selects function AD2 0x3 Selects fun...

Page 58: ...istor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 Reserved 1 7 A...

Page 59: ...pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 7...

Page 60: ...reserved User manual Rev 1 20 October 2010 60 of 258 NXP Semiconductors UM10429 Chapter 7 LPC1102 I O Configuration 5 HYS Hysteresis 0 0 Disable 1 Enable 7 6 Reserved 11 31 8 Reserved 0 Table 57 IOCON...

Page 61: ...t A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 I O PIO0_0 General purpose digital input output pi...

Page 62: ...d I O PIO1_0 General purpose digital input output pin I AD1 A D converter input 1 I CT32B1_CAP0 Capture input 0 for 32 bit timer 1 R PIO1_1 AD2 CT32B1_MAT0 C4 4 no I PU R Reserved I O PIO1_1 General p...

Page 63: ...alf word operations at word addresses UM10429 Chapter 9 LPC1102 General Purpose I O GPIO Rev 1 20 October 2010 User manual Table 59 GPIO configuration Part Package GPIO port 0 GPIO port 1 GPIO port 2...

Page 64: ...r digital function A read returns the current state of the pin If a pin is configured as another digital function input or output a write to the GPIOnDATA register has no effect on the pin level A rea...

Page 65: ...rrupt on pin x as level or edge sensitive x 0 to 11 0 Interrupt on pin PIOn_x is configured as edge sensitive 1 Interrupt on pin PIOn_x is configured as level sensitive 0x00 R W 31 12 Reserved Table 6...

Page 66: ...pins has been generated or that the interrupt is masked GPIOMIS is the state of the interrupt after masking The register is read only 9 3 9 GPIO interrupt clear register This register allows software...

Page 67: ...e address bit i 2 associated with the GPIO port bit i i 0 to 11 to be written is HIGH the value of the GPIODATA register bit i is updated If the address bit i 2 is LOW the corresponding GPIODATA regis...

Page 68: ...ead operation If the address bit associated with the GPIO data bit is HIGH the value is read If the address bit is LOW the GPIO data bit is read as 0 Reading a port DATA register yields the state of p...

Page 69: ...UARTCLKDIV register Table 21 10 3 Features 16 byte receive and transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate...

Page 70: ...1 0x00 U0IER R W 0x004 Interrupt Enable Register Contains individual interrupt enable bits for the 7 potential UART interrupts DLAB 0 0x00 U0IIR RO 0x008 Interrupt ID Register Identifies which interr...

Page 71: ...ansmit The Divisor Latch Access Bit DLAB in U0LCR must be zero in order to access the U0THR The U0THR is always Write Only 10 5 3 UART Divisor Latch LSB and MSB Registers DLAB 1 The UART Divisor Latch...

Page 72: ...aud rate of the UART 0x00 31 8 Reserved Table 76 UART Interrupt Enable Register U0IER address 0x4000 8004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBRIE RBR Interrupt Ena...

Page 73: ...e Register U0IER address 0x4000 8004 when DLAB 0 bit description continued Bit Symbol Value Description Reset value Table 77 UART Interrupt Identification Register U0IIR address 0x4004 8008 Read Only...

Page 74: ...d The UART RDA interrupt U0IIR 3 1 010 shares the second level priority with the CTI interrupt U0IIR 3 1 110 The RDA is activated when the UART Rx FIFO reaches the trigger level defined in U0FCR7 6 an...

Page 75: ...HRE 1 and there have not been at least two characters in the U0THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to U0THR without a THRE interrupt t...

Page 76: ...o U0FCR 1 will clear all bytes in UART Rx FIFO reset the pointer logic This bit is self clearing 2 TXFIFO RES TX FIFO Reset 0 0 No impact on either of UART FIFOs 1 Writing a logic 1 to U0FCR 2 will cl...

Page 77: ...ble break transmission Output pin UART TXD is forced to logic 0 when U0LCR 6 is active high 7 DLAB Divisor Latch Access Bit DLAB 0 0 Disable access to Divisor Latches 1 Enable access to Divisor Latche...

Page 78: ...ing Error Note A framing error is associated with the character at the top of the UART RBR FIFO 0 0 Framing error status is inactive 1 Framing error status is active 4 BI Break Interrupt When RXD1 is...

Page 79: ...gister is read and there are no subsequent errors in the UART FIFO 0 0 U0RBR contains no UART RX errors or U0FCR 0 0 1 UART RBR contains at least one UART RX error 31 8 Reserved Table 81 UART Line Sta...

Page 80: ...e measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the UART Rx pin The auto baud function can generate two interrupts The U0IIR ABTOInt in...

Page 81: ...ate is switched to the highest rate 2 A falling edge on UART Rx pin triggers the beginning of the start bit The rate measuring counter will start counting UART_PCLK cycles 3 During the receipt of the...

Page 82: ...the APB clock and generates an output clock according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL 0 and DLM 0 the value of the DLL register must b...

Page 83: ...these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided 10 5 13 1 Baud rate calculation UART...

Page 84: ...iversal Asynchronous Transmitter UART Fig 11 Algorithm for setting UART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL es...

Page 85: ...he UART s baud rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 10 5 14 UART Transmit Enable Register In addition to being equipped with full hardware flow co...

Page 86: ...a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of character...

Page 87: ...byte is detected parity bit 1 it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated The processor can then read the address byte and decide whether or not to enable the r...

Page 88: ...ART RX Shift Register U0RSR accepts valid characters via RXD After a valid character is assembled in the U0RSR it is passed to the UART RX Buffer Register FIFO to await access by the CPU or host via t...

Page 89: ...October 2010 89 of 258 NXP Semiconductors UM10429 Chapter 10 LPC1102 Universal Asynchronous Transmitter UART Fig 12 UART block diagram APB INTERFACE U0LCR U0RX DDIS U0LSR U0FCR U0BRG U0TX INTERRUPT PA...

Page 90: ...ing the SPI because the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package Once the SPI is enabled the serial wire debugger is no longer available 11 3 Featu...

Page 91: ...s a bus master it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the data has been sent The active state of this signal can be hi...

Page 92: ...s master slave and other modes 0 SSP0DR R W 0x008 Data Register Writes fill the transmit FIFO and reads empty the receive FIFO 0 SSP0SR RO 0x00C Status Register 0x0000 0003 SSP0CPSR R W 0x010 Clock Pr...

Page 93: ...r captures serial data on the second clock transition of the frame that is the transition back to the inter frame state of the clock line 15 8 SCR Serial Clock Rate The number of prescaler output cloc...

Page 94: ...SSP Data Register SSP0DR address 0x4004 0008 bit description Bit Symbol Description Reset Value 15 0 DATA Write software can write data to be sent in a future frame to this register whenever the TNF...

Page 95: ...t Mask Set Clear Register This register controls whether each of the four possible interrupt conditions in the SPI controller are enabled Note that ARM uses the word masked in the opposite sense from...

Page 96: ...when a Receive Time out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time out period The time out period is the same for master and slave mod...

Page 97: ...ull and this interrupt is enabled 0 1 RTMIS This bit is 1 if the Rx FIFO is not empty has not been read for a time out period and this interrupt is enabled The time out period is the same for master a...

Page 98: ...data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been l...

Page 99: ...14 In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SPI SSP is enabled and there is valid data within t...

Page 100: ...0 CPHA 1 is shown in Figure 15 which covers both single and continuous transfers In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad...

Page 101: ...agated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period a...

Page 102: ...ive transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits...

Page 103: ...OW CS is forced HIGH The transmit data line SO is arbitrarily forced LOW A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained in...

Page 104: ...control byte of the next frame follows directly after the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK aft...

Page 105: ...nal interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to three CT16B0 or two CT16B1 external outputs corre...

Page 106: ...a CT16B1 Output no outputs available Table 101 Register overview 16 bit counter timer 0 CT16B0 base address 0x4000 C000 Name Access Address offset Description Reset value 1 TMR16B0IR R W 0x000 Interru...

Page 107: ...6B1TCR R W 0x004 Timer Control Register TCR The TCR is used to control the Timer Counter functions The Timer Counter can be disabled or reset through the TCR 0 TMR16B1TC R W 0x008 Timer Counter TC The...

Page 108: ...use an interrupt but a Match register can be used to detect an overflow if needed 0x040 0x06C Reserved 0x070 Reserved TMR16B1PWMC R W 0x074 PWM Control Register PWMCON The PWMCON enables PWM mode for...

Page 109: ...PCLKs when PR 1 etc 12 7 6 Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of...

Page 110: ...Enabled 0 Disabled 5 MR1S Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches the TC 0 1 Enabled 0 Disabled 6 MR2I Interrupt on MR2 an interrupt is generated when MR2...

Page 111: ...h pins CT16B0_MAT 2 0 and CT16B1_MAT 1 0 If the match outputs are configured as PWM output in the PWMCON registers Section 12 7 9 the function of the external match registers is determined by the PWM...

Page 112: ...toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output Note that on counter timer 0 this match channel is not pinned out This bit is driven to the CT16B1_MAT2 pin if...

Page 113: ...rol 3 Determines the functionality of External Match 3 00 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out 10 Set the corresponding External...

Page 114: ...pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero an...

Page 115: ...ows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer en...

Page 116: ...Architecture The block diagram for counter timer0 and counter timer1 is shown in Figure 24 Fig 24 16 bit counter timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COU...

Page 117: ...it capture channel that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continu...

Page 118: ...ddress 13 6 Pin description Table 113 gives a brief summary of each of the counter timer related pins 13 7 Register description 32 bit counter timer0 contains the registers shown in Table 114 and 32 b...

Page 119: ...atch Control Register MCR The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs 0 TMR32B0MR0 R W 0x018 Match Register 0 MR0 MR0 can be enabled through the...

Page 120: ...gister 1 MR1 See MR0 description 0 TMR32B1MR2 R W 0x020 Match Register 2 MR2 See MR0 description 0 TMR32B1MR3 R W 0x024 Match Register 3 MR3 See MR0 description 0 TMR32B1CCR R W 0x028 Capture Control...

Page 121: ...bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship between the resolution of the timer and the max...

Page 122: ...prescale counter value 0 Table 121 Match Control Register TMR32B0MCR address 0x4001 4014 and TMR32B1MCR address 0x4001 8014 bit description Bit Symbol Value Description Reset value 0 MR0I Interrupt o...

Page 123: ...he Timer number 0 or 1 8 MR2S Stop on MR2 the TC and PC will be stopped and TCR 0 will be set to 0 if MR2 matches the TC 0 1 Enabled 0 Disabled 9 MR3I Interrupt on MR3 an interrupt is generated when M...

Page 124: ...both control and status of the external match pins CAP32Bn_MAT 3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Sectio...

Page 125: ...hing Bits EMR 9 8 control the functionality of this output This bit is driven to the CT32B0_MAT2 CT16B1_MAT2 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 0 3 EM3 External...

Page 126: ...uccessive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of...

Page 127: ...Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field selects which rising PCLK edges can increment Timer s Prescale Counter PC or clear PC and increment Timer Counter TC Tim...

Page 128: ...mined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuo...

Page 129: ...after the timer reached the match value Figure 27 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock...

Page 130: ...nter timers CT32B0 1 Fig 28 32 bit counter timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REGISTER 2 M...

Page 131: ...Watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate Watchdog reset Programmable 24 bit timer with internal pre scaler Selecta...

Page 132: ...must be cleared by software 14 6 WDT clocking The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock s...

Page 133: ...reset or interrupt will occur any time the watchdog is running and has an operating clock source Any clock source works in Sleep mode and if a watchdog interrupt occurs in Sleep mode it will wake up...

Page 134: ...enerated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence Interrupts should be disabled during the feed sequence An abort condition will occur if an i...

Page 135: ...K cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read by the CPU 14 8 Block diagram The block diagram of the Watchdog is shown below in the...

Page 136: ...The SysTick timer is an integral part of the Cortex M0 The SysTick timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software Sin...

Page 137: ...to tbd The block diagram of the SysTick timer is shown below in the Figure 30 15 6 Register description The systick timer registers are located on the ARM Cortex M0 private peripheral bus see Figure...

Page 138: ...ftware 15 6 4 System Timer Calibration value register SYST_CALIB 0xE000 E01C The value of the SYST_CALIB register is driven by the value of the SYSTCKCAL register in the system configuration block see...

Page 139: ...rval 2 Clear the SYST_CVR register by writing to it This ensures that the timer will count from the SYST_RVR value rather than an arbitrary value when the timer is enabled 3 Program the SYST_SCR regis...

Page 140: ...r single or multiple inputs Optional conversion on transition on input pin or Timer Match signal Individual result registers for each A D channel to reduce interrupt overhead 16 4 Pin description Tabl...

Page 141: ...D conversion can occur 0x0000 0000 AD0GDR R W 0x004 A D Global Data Register Contains the result of the most recent A D conversion NA 0x008 Reserved AD0INTEN R W 0x00C A D Interrupt Enable Register T...

Page 142: ...og source a slower clock may be desirable 0 16 BURST Burst mode Remark If BURST is set to 1 the ADGINTEN bit in the AD0INTEN register Table 144 must be set to 0 0 0 Software controlled mode Conversion...

Page 143: ...y when the START field contains 010 111 In these cases Start conversion on a falling edge on the selected CAP MAT signal 0 0 Start conversion on a rising edge on the selected CAP MAT signal 31 28 Rese...

Page 144: ...in future compatible A D converters that can convert more channels 0 30 OVERR UN This bit is 1 in burst mode if the results of one or more conversions was were lost and overwritten before the convers...

Page 145: ...ag in ADDR to generate an interrupt When 0 only the individual A D channels enabled by ADINTEN 4 0 will generate interrupts Remark This bit must be set to 0 in burst mode BURST 1 in the AD0CR register...

Page 146: ...for interrupts via the ADINTEN register are one Software can use the Interrupt Enable bit in the interrupt controller that corresponds to the ADC to control whether this results in an interrupt The re...

Page 147: ...ans to accomplish programming of the flash memory via UART This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash...

Page 148: ...arity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII...

Page 149: ...3 4 Boot process flowchart 1 For details on handling the crystal frequency see Section 17 6 8 Reinvoke ISP IAP on page 166 Fig 31 Boot process flowchart RESET INITIALIZE RECEIVE CRYSTAL FREQUENCY RUN...

Page 150: ...PU requests a read from user s Flash both 128 bits of raw data containing the specified memory location and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetch...

Page 151: ...Copy RAM to flash command can not write to Sector 0 Erase command can erase Sector 0 only when all sectors are selected for erase Compare command is disabled Read Memory command is disabled This mode...

Page 152: ...Return_Code CR LF Response_0 CR LF Response_1 CR LF Response_n CR LF Data Data only for Read commands 17 4 3 UART ISP data format The data stream is in UU encoded format The UU encode algorithm conver...

Page 153: ...uring UART ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset 17 4 7 Interrupts during IAP The on chip flash memory is not accessible during erase w...

Page 154: ...rite to RAM W start address number of bytes Table 155 Read Memory R address number of bytes Table 156 Prepare sector s for write operation P start sector number end sector number Table 157 Copy RAM to...

Page 155: ...s If the check sum matches the ISP command handler responds with OK CR LF to continue further transmission If the check sum does not match the ISP command handler responds with RESEND CR LF In respons...

Page 156: ...ain 17 5 6 Prepare sector s for write operation start sector number end sector number UART ISP This command makes flash write erase operation a two step process Return Code CMD_SUCCESS ADDR_ERROR Addr...

Page 157: ...sh memories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 1...

Page 158: ...scription This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the...

Page 159: ...ed using this command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 CR LF erases the flash sectors 2 and 3 Table 161 UART ISP Blank check...

Page 160: ...ss2 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should be a multiple of 4 Return Code CMD_SUCCE...

Page 161: ...been completely and successfully executed 1 INVALID_COMMAND Invalid command 2 SRC_ADDR_ERROR Source address is not on word boundary 3 DST_ADDR_ERROR Destination address is not on a correct boundary 4...

Page 162: ...and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap_entry Setting function pointer iap_entry IAP IAP_L...

Page 163: ...69 Copy RAM to flash 5110 Table 170 Erase sector s 5210 Table 171 Blank check sector s 5310 Table 172 Read Part ID 5410 Table 173 Read Boot code version 5510 Table 174 Compare 5610 Table 175 Reinvoke...

Page 164: ...s for write operation Table 170 IAP Copy RAM to flash command Command Copy RAM to flash Input Command code 5110 Param0 DST Destination flash address where data bytes are to be written This address sh...

Page 165: ...y The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Table 172 IAP Blank check sector s command Command Blank check sector s Input Com...

Page 166: ...word boundary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 Return Code C...

Page 167: ...sult0 The first 32 bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word Description This command is used to read the unique ID Tab...

Page 168: ...neration completes independently While signature generation is in progress the flash memory cannot be accessed for other purposes and an attempted read will cause a wait state to be asserted until sig...

Page 169: ...ble 183 show the bit assignments in the FMSSTART and FMSSTOP registers respectively Table 181 Register overview FMC base address 0x4003 C000 Name Access Address offset Description Reset value Referenc...

Page 170: ...ration can be checked by polling the SIG_DONE bit in FMSTAT SIG_DONE should be cleared via the FMSTATCLR register before starting a signature generation operation otherwise the status might indicate c...

Page 171: ...is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG_DONE bit in F...

Page 172: ...e corrected data read from the flash The 128 bit signature reflects flash parity bits and check bit values Content verification The signature as it is read from the FMSW0 to FMSW3 registers must be eq...

Page 173: ...0 is configured to support up to four breakpoints and two watchpoints 18 4 Description Debugging with the LPC1102 uses the Serial Wire Debug mode 18 5 Pin description The tables below indicate the var...

Page 174: ...during debug Another issue is that debug mode changes the way in which reduced power modes work internal to the ARM Cortex M0 CPU and this ripples through the entire system These differences mean tha...

Page 175: ...processor family The Cortex M0 processor is built on a highly area and power optimized 32 bit processor core with a 3 stage pipeline von Neumann architecture The processor delivers exceptional energy...

Page 176: ...tching from one ISR to another To optimize low power designs the NVIC integrates with the sleep modes that include a Deep sleep function that enables the entire device to be rapidly powered down 19 2...

Page 177: ...cation software The processor enters Thread mode when it comes out of reset Handler mode Used to handle exceptions The processor returns to Thread mode when it has finished all exception processing 19...

Page 178: ...se 0 Main Stack Pointer MSP This is the reset value 1 Process Stack Pointer PSP Fig 36 Processor core register set Table 192 Core register set summary Name Type 1 Reset value Description R0 R12 RW Unk...

Page 179: ...s Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status Register EPSR These registers are mutually exclusive bitfields in the 3...

Page 180: ...egative zero carry or borrow and overflow flags Interrupt Program Status Register The IPSR contains the exception number of the current Interrupt Service Routine ISR See the register summary in Table...

Page 181: ...abandons execution of the instruction After servicing the interrupt the processor restarts execution of the instruction from the beginning 19 3 1 3 6 Exception mask register The exception mask regist...

Page 182: ...ex M0 processor supports interrupts and system exceptions The processor and the Nested Vectored Interrupt Controller NVIC prioritize and handle all exceptions An interrupt or exception changes the nor...

Page 183: ...ation of CMSIS compliant software components from various middleware vendors Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals Th...

Page 184: ...memory type and attributes determine the behavior of accesses to the region The memory types are Normal The processor can re order transactions for efficiency or perform speculative reads Device The p...

Page 185: ...r in which the accesses complete matches the program order of the instructions providing any re ordering does not affect the behavior of the instruction sequence Normally if correct program execution...

Page 186: ...MB The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions See Section 19 19 4 7 3 DSB The Data Synchronization Barrier DSB...

Page 187: ...dated memory map Memory accesses to Strongly ordered memory such as the System Control Block do not require the use of DMB instructions The processor preserves transaction order relative to all other...

Page 188: ...other than reset It is permanently enabled and has a fixed priority of 2 NMIs cannot be masked or prevented from activation by any other exception preempted by any exception other than Reset HardFault...

Page 189: ...r more information about HardFaults see Section 19 19 3 4 19 3 3 3 Exception handlers The processor handles exceptions using Interrupt Service Routines ISRs Interrupts IRQ0 to IRQ31 are the exceptions...

Page 190: ...ult and NMI If software does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For information about configuring exception priorities see Section 19 19...

Page 191: ...exceptions are called nested exceptions See Section 19 19 3 3 6 1 for more information Return This occurs when the exception handler is completed and there is no pending exception with sufficient pri...

Page 192: ...executing the exception handler At the same time the processor writes an EXC_RETURN value to the LR This indicates which stack pointer corresponds to the stack frame and what operation mode the proce...

Page 193: ...r on a vector fetch execution of an Undefined instruction execution of an instruction when not in Thumb State as a result of the T bit being previously cleared to 0 an attempted load or store to an un...

Page 194: ...ode after such an event A program might have an idle loop to put the processor back in to sleep mode 19 3 5 1 1 Wait for interrupt The Wait For Interrupt instruction WFI causes immediate entry to slee...

Page 195: ...f an interrupt arrives that is enabled and has a higher priority than current exception priority the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to z...

Page 196: ...egative N Z C V Section 19 19 4 5 4 CMP Rn Rm imm Compare N Z C V Section 19 19 4 5 4 CPSID i Change Processor State Disable Interrupts Section 19 19 4 7 2 CPSIE i Change Processor State Enable Interr...

Page 197: ...d halfword Section 19 19 4 5 7 RORS Rd Rn Rs Rotate Right N Z C Section 19 19 4 5 3 RSBS Rd Rn 0 Reverse Subtract N Z C V Section 19 19 4 5 1 SBCS Rd Rn Rm Subtract with Carry N Z C V Section 19 19 4...

Page 198: ...on register When there is a destination register in the instruction it is usually specified before the other operands 19 4 3 2 Restrictions when using PC or SP Many instructions are unable to use or h...

Page 199: ...s update the carry flag except when the specified shift length is 0 The following sub sections describe the various shift operations and how they affect the carry flag In these descriptions Rm is the...

Page 200: ...LSL Logical shift left by n bits moves the right hand 32 n bits of the register Rm to the left by n places into the left hand 32 n bits of the result and it sets the right hand n bits of the result to...

Page 201: ...gnment An aligned access is an operation where a word aligned address is used for a word or multiple word access or where a halfword aligned address is used for a halfword access Byte accesses are alw...

Page 202: ...ative cleared to 0 otherwise Z Set to 1 when the result of the operation was zero cleared to 0 otherwise C Set to 1 when the operation resulted in a carry cleared to 0 otherwise V Set to 1 when the op...

Page 203: ...r same unsigned CC or LO C 0 Lower unsigned MI N 1 Negative PL N 0 Positive or zero VS V 1 Overflow VC V 0 No overflow HI C 1 and Z 0 Higher unsigned LS C 0 or Z 1 Lower or same unsigned GE N V Greate...

Page 204: ...3 Restrictions In this instruction Rd must specify R0 R7 The data value addressed must be word aligned and within 1020 bytes of the current PC 19 4 4 1 4 Condition flags This instruction does not cha...

Page 205: ...R and STR using SP as the base register 0 and 124 and an integer multiple of four for LDR and STR using R0 R7 as the base register 0 and 62 and an integer multiple of two for LDRH and STRH 0 and 31 fo...

Page 206: ...In these instructions Rt Rn and Rm must only specify R0 R7 the computed memory address must be divisible by the number of bytes in the load or store see Section 19 19 4 3 4 19 4 4 3 4 Condition flags...

Page 207: ...ks STMIA and STMEA are synonyms for STM STMIA refers to the base register being Incremented After each access STMEA refers to its use for pushing data onto Empty Ascending stacks 19 4 4 5 2 Operation...

Page 208: ...ster ranges It must be comma separated if it contains more than one register or register range 19 4 4 6 2 Operation PUSH stores registers on the stack with the lowest numbered register using the lowes...

Page 209: ...ection 19 19 4 5 2 ASRS Arithmetic Shift Right Section 19 19 4 5 3 BICS Bit Clear Section 19 19 4 5 2 CMN Compare Negative Section 19 19 4 5 4 CMP Compare Section 19 19 4 5 4 EORS Exclusive OR Section...

Page 210: ...Rm adding a further one if the carry flag is set places the result in the register specified by Rd and updates the N Z C and V flags The ADD instruction adds the value in Rn to the value in Rm or an i...

Page 211: ...nd R6 96 bit subtraction SUBS R4 R4 R1 subtract the least significant words SBCS R5 R5 R2 subtract the middle words with carry SBCS R6 R6 R3 subtract the most significant words with carry The followin...

Page 212: ...sive OR operations on the values in Rn and Rm The BIC instruction performs an AND operation on the bits in Rn with the logical negation of the corresponding bits in the value of Rm The condition code...

Page 213: ...eft logical shift left logical shift right or a right rotation of the bits in the register Rm by the number of places specified by the immediate imm or the value in the least significant byte of the r...

Page 214: ...ut do not write the result to a register The CMP instruction subtracts either the value in the register specified by Rm or the immediate imm from the value in Rn and updates the flags This is the same...

Page 215: ...3 Restrictions In these instructions Rd and Rm must only specify R0 R7 When Rd is the PC in a MOV instruction Bit 0 of the result is discarded A branch occurs to the address created by forcing bit 0...

Page 216: ...pend on whether the operands are signed or unsigned 19 4 5 6 3 Restrictions In this instruction Rd Rn and Rm must only specify R0 R7 Rd must be the same as Rm 19 4 5 6 4 Condition flags This instructi...

Page 217: ...se byte order of value in R7 and write it to R3 REV16 R0 R0 Reverse byte order of each 16 bit halfword in R0 REVSH R0 R5 Reverse signed halfword 19 4 5 8 SXT and UXT Sign extend and Zero extend 19 4 5...

Page 218: ...flags based on the result but does not write the result to a register The TST instruction performs a bitwise AND operation on the value in Rn and the value in Rm This is the same as the ANDS instructi...

Page 219: ...ctions write the address of the next instruction to LR the link register R14 The BX and BLX instructions result in a HardFault exception if bit 0 of Rm is 0 BL and BLX instructions also set bit 0 of t...

Page 220: ...ion call BLX R0 Branch with link and exchange Call to a address stored in R0 BEQ labelD Conditionally branch to labelD if last flag setting instruction set the Z flag else do not branch 19 4 7 Miscell...

Page 221: ...ht also produce a HardFault or go in to lockup if a debugger is not attached when a BKPT instruction is executed See Section 19 19 3 4 1 for more information 19 4 7 1 3 Restrictions There are no restr...

Page 222: ...all explicit memory accesses that appear in program order before the DMB instruction are observed before any explicit memory accesses that appear in program order after the DMB instruction DMB does no...

Page 223: ...ruction has been completed 19 4 7 5 3 Restrictions There are no restrictions 19 4 7 5 4 Condition flags This instruction does not change the flags 19 4 7 5 5 Examples ISB Instruction Synchronisation B...

Page 224: ...SR EPSR IEPSR IAPSR EAPSR PSR MSP PSP PRIMASK or CONTROL 19 4 7 7 2 Operation MSR updates one of the special registers with the value from the register specified by Rn See Section 19 19 4 7 6 19 4 7 7...

Page 225: ...ocessor system It also sets the local event register see Section 19 19 3 5 See also Section 19 19 4 7 11 19 4 7 9 3 Restrictions There are no restrictions 19 4 7 9 4 Condition flags This instruction d...

Page 226: ...vents occurs an exception unless masked by the exception mask registers or the current priority level an exception enters the Pending state if SEVONPEND in the System Control Register is set a Debug E...

Page 227: ...lags This instruction does not change the flags 19 4 7 12 5 Examples WFI Wait for interrupt 19 5 Peripherals 19 5 1 About the ARM Cortex M0 The address map of the Private peripheral bus PPB is In regi...

Page 228: ...ows which interrupts are enabled See the register summary in Table 213 for the register attributes The bit assignments are Table 213 NVIC register summary Address Name Type Reset value Description 0xE...

Page 229: ...bit assignments are 19 5 2 4 Interrupt Set pending Register The ISPR forces interrupts into the pending state and shows which interrupts are pending See the register summary in Table 19 213 for the re...

Page 230: ...rity field for each interrupt These registers are only word accessible See the register summary in Table 19 213 for their attributes Each register holds four priority fields as shown Table 218 ICPR bi...

Page 231: ...tects the interrupt the peripheral must assert the interrupt signal for at least one clock cycle during which the NVIC detects the pulse and latches the interrupt When the processor enters the ISR it...

Page 232: ...ccesses to NVIC registers An interrupt can enter pending state even if it is disabled Disabling an interrupt only prevents the processor from taking that interrupt 19 5 2 8 1 NVIC programming hints So...

Page 233: ...exceptions indicates the exception number of the exception being processed whether there are preempted active exceptions the exception number of the highest priority pending exception Table 221 Summa...

Page 234: ...r enters the NMI exception handler as soon as it detects a write of 1 to this bit Entering the handler then clears this bit to 0 This means a read of this bit by the NMI exception handler returns 1 on...

Page 235: ...ield otherwise the processor ignores the write The bit assignments are 25 PENDSTCLR WO SysTick exception clear pending bit Write 0 no effect 1 removes the pending state from the SysTick exception This...

Page 236: ...g to the register you must write 0 to this bit otherwise behavior is Unpredictable 0 Reserved Table 225 SCR bit assignments Bits Name Function 31 5 Reserved 4 SEVONPEND Send Event on Pending bit 0 onl...

Page 237: ...pe IRQn void NVIC_SetPriority IRQn_Type IRQn uint32_t priority The input parameter IRQn is the IRQ number see Table 19 200 for more information The system fault handlers and the priority field and reg...

Page 238: ...zero the timer will be maintained with a current value of zero after it is reloaded with this value This mechanism can be used to disable the feature independently from the timer enable bit A write t...

Page 239: ...s use a RELOAD value of N 1 For example if the SysTick interrupt is required every 100 clock pulses set RELOAD to 99 19 5 4 3 SysTick Current Value Register The SYST_CVR contains the current value of...

Page 240: ...initialization sequence for the SysTick counter is 1 Program reload value 2 Clear current value 3 Program Control and Status register 19 6 Cortex M0 instruction summary Table 233 SYST_CVR bit assignme...

Page 241: ...Rd Rm 1 Move NOT MVNS Rd Rm 1 AND test TST Rn Rm 1 Shift Logical shift left by immediate LSLS Rd Rm shift 1 Logical shift left by register LSLS Rd Rd Rs 1 Logical shift right by immediate LSRS Rd Rm...

Page 242: ...1 N 2 Push with link register PUSH loreglist LR 1 N 2 Pop Pop POP loreglist 1 N 2 Pop and return POP loreglist PC 4 N 3 Branch Conditional B cc label 1 or 3 4 Unconditional B label 3 With link BL lab...

Page 243: ...XP B V 2010 All rights reserved User manual Rev 1 20 October 2010 243 of 258 NXP Semiconductors UM10429 Chapter 19 Appendix LPC1102 ARM Cortex M0 reference 5 Cycle count depends on core and debug conf...

Page 244: ...e Manual UM10429 Chapter 20 LPC1102 Supplementary information Rev 1 20 October 2010 User manual Table 236 Abbreviations Acronym Description ADC Analog to Digital Converter AHB Advanced High performanc...

Page 245: ...ed or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reaso...

Page 246: ...Table 24 WDT clock divider register WDTCLKDIV address 0x4004 80D8 bit description 21 Table 25 POR captured PIO status registers 0 PIOPORCAP0 address 0x4004 8100 bit description 22 Table 26 BOD control...

Page 247: ...RT Divisor Latch MSB Register U0DLM address 0x4000 8004 when DLAB 1 bit description 72 Table 76 UART Interrupt Enable Register U0IER address 0x4000 8004 when DLAB 0 bit description 72 Table 77 UART In...

Page 248: ...scription 123 Table 124 Capture registers TMR32B1CR0 addresses 0x4001 802C bit description 124 Table 125 External Match Register TMR32B0EMR address 0x4001 403C and TMR32B1EMR address0x4001 803C bit de...

Page 249: ...0x0x4003 CFE8 bit description 170 Table 190 Serial Wire Debug pin description 172 Table 191 Summary of processor mode and stack use options 176 Table 192 Core register set summary 177 Table 193 PSR re...

Page 250: ...up and hold details 104 Fig 21 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 115 Fig 22 A timer cycle in which PR 2 MRx 6...

Page 251: ...r 21 3 5 19 WDT clock divider register 21 3 5 20 POR captured PIO status register 0 21 3 5 21 BOD control register 22 3 5 22 System tick counter calibration register 23 3 5 23 Start logic edge control...

Page 252: ...CON_PIOn 53 Chapter 8 LPC1102 Pin configuration 8 1 How to read this chapter 61 8 2 Pin configuration 61 Chapter 9 LPC1102 General Purpose I O GPIO 9 1 How to read this chapter 63 9 2 Introduction 63...

Page 253: ...and hold time requirements on CS with respect to SK in Microwire mode 104 Chapter 12 LPC1102 16 bit counter timers CT16B0 1 12 1 How to read this chapter 105 12 2 Basic configuration 105 12 3 Features...

Page 254: ...ures 140 16 4 Pin description 140 16 5 ADC clocking 141 16 6 Register description 141 16 6 1 A D Control Register 141 16 6 2 A D Global Data Register 143 16 6 3 A D Status Register 143 16 6 4 A D Inte...

Page 255: ...x LPC1102 ARM Cortex M0 reference 19 1 Introduction 174 19 2 About the Cortex M0 processor and core peripherals 174 19 2 1 System level interface 175 19 2 2 Integrated configurable debug 175 19 2 3 Co...

Page 256: ...ADD RSB SBC and SUB 209 19 4 5 1 1 Syntax 209 19 4 5 1 2 Operation 209 19 4 5 1 3 Restrictions 210 19 4 5 1 4 Examples 210 19 4 5 2 AND ORR EOR and BIC 210 19 4 5 2 1 Syntax 211 19 4 5 2 2 Operation...

Page 257: ...4 7 11 4 Condition flags 225 19 4 7 11 5 Examples 225 19 4 7 12 WFI 225 19 4 7 12 1 Syntax 225 19 4 7 12 2 Operation 226 19 4 7 12 3 Restrictions 226 19 4 7 12 4 Condition flags 226 19 4 7 12 5 Examp...

Page 258: ...ase visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 20 October 2010 Document identifier UM10429 Please be aware that important notices...

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