UM10429
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User manual
Rev. 1 — 20 October 2010
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NXP Semiconductors
UM10429
Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
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a disabled interrupt sets the state of that interrupt to pending.
19.5.2.5 Interrupt Clear-pending Register
The ICPR removes the pending state from interrupts, and shows which interrupts are
pending. See the register summary in
for the register attributes.
The bit assignments are:
Remark:
Writing 1 to an ICPR bit does not affect the active state of the corresponding
interrupt.
19.5.2.6 Interrupt Priority Registers
The IPR0-IPR7 registers provide an 2-bit priority field for each interrupt. These registers
are only word-accessible. See the register summary in
for their attributes.
Each register holds four priority fields as shown:
Table 218. ICPR bit assignments
Bits
Name
Function
[31:0]
CLRPEND
Interrupt clear-pending bits.
Write:
0 = no effect
1 = removes pending state an interrupt.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
Fig 47. IPR register
PRI_31
31
24 23
16 15
8 7
0
PRI_30
PRI_29
PRI_28
IPR7
PRI_(4n+3)
PRI_(4n+2)
PRI_(4n+1)
PRI_(4n)
IPR
n
PRI_3
PRI_2
PRI_1
PRI_0
IPR0
. . .
. . .
. . .
. . .
Table 219. IPR bit assignments
Bits
Name
Function
[31:24]
Priority, byte offset 3
Each priority field holds a priority value, 0-3. The lower the
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:6] of each field, bits
[5:0] read as zero and ignore writes.
[23:16]
Priority, byte offset 2
[15:8]
Priority, byte offset 1
[7:0]
Priority, byte offset 0
