NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 142 of 258
NXP Semiconductors
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Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
Table 141. A/D Control Register (AD0CR - address 0x4001 C000) bit description
Bit Symbol Value Description Reset
Value
4:0 SEL Selects which of the AD4:0 pins is (are) to be sampled and converted. Bit 0 selects Pin
AD0, bit 1 selects pin AD1,..., and bit 4 selects pin AD4.
In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one
of these bits should be 1.
In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any
or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL =
0x01). 0x00
7:5 - Reserved
15:8 CLKDIV The APB clock (PCLK) is divided by 1 to produce the clock for the ADC, which
should be less than or equal to 4.5 MHz. Typically, software should program the smallest
value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such
as a high-impedance analog source) a slower clock may be desirable. 0
16 BURST Burst mode
Remark: If BURST is set to 1 , the ADGINTEN bit in the AD0INTEN register ( Table 144 )
must be set to 0.
0
0 Software-controlled mode: Conversions are software-controlled and require 11 clocks.
1 Hardware scan mode: The AD converter does repeated conversions at the rate selected
by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL
field. The first conversion after the start corresponds to the least-significant bit set to 1 in
the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated
conversions can be terminated by clearing this bit, but the conversion in progress when
this bit is cleared will be completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
19:17 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the
number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks
(10 bits) and 4 clocks (3 bits). 000
0x0 11 clocks / 10 bits
0x1 10 clocks / 9 bits
0x2 9 clocks / 8 bits
0x3 8 clocks / 7 bits
0x4 7 clocks / 6 bits
0x5 6 clocks / 5 bits
0x6 5 clocks / 4 bits
0x7 4 clocks / 3 bits
23:20 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined. NA