UM10429
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User manual
Rev. 1 — 20 October 2010
145 of 258
NXP Semiconductors
UM10429
Chapter 16: LPC1102 Analog-to-Digital Converter (ADC)
16.6.5 A/D Data Registers
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
16.7 Operation
16.7.1 Hardware-triggered conversion
If the BURST bit in the ADCR0 is 0 and the START field contains 010-111, the A/D
converter will start a conversion when a transition occurs on a selected pin or timer match
signal.
Table 144. A/D Interrupt Enable Register (AD0INTEN - address 0x4001 C00C) bit description
Bit
Symbol
Description
Reset
Value
4:0
ADINTEN 4:0
These bits allow control over which A/D channels generate
interrupts for conversion completion. When bit 0 is one, completion
of a conversion on A/D channel 0 will generate an interrupt, when bit
1 is one, completion of a conversion on A/D channel 1 will generate
an interrupt, etc.
0x00
7:5
-
Reserved.
-
8
ADGINTEN
When 1, enables the global DONE flag in ADDR to generate an
interrupt. When 0, only the individual A/D channels enabled by
ADINTEN 4:0 will generate interrupts.
Remark:
This bit must be set to 0 in burst mode (BURST = 1 in the
AD0CR register).
1
31:9 Unused
Unused, always 0.
0
Table 145. A/D Data Registers (AD0DR0 to AD0DR4 - addresses 0x4001 C010 to
0x4001 C020) bit description
Bit
Symbol
Description
Reset
Value
5:0
Unused
Unused, always 0.
These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution ADCs.
0
15:6
V_VREF
When DONE is 1, this field contains a binary fraction representing the
voltage on the ADn pin, divided by the voltage on the V
REF
pin. Zero in
the field indicates that the voltage on the ADn pin was less than, equal
to, or close to that on V
REF
, while 0x3FF indicates that the voltage on
AD input was close to, equal to, or greater than that on V
REF
.
NA
29:16 Unused
These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field.
0
30
OVERRUN This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that produced
the result in the V_VREF bits.This bit is cleared by reading this
register.
0
31
DONE
This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read.
0
