UM10429
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User manual
Rev. 1 — 20 October 2010
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NXP Semiconductors
UM10429
Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
19.5.2.3 Interrupt Clear-enable Register
The ICER disables interrupts, and show which interrupts are enabled. See the register
summary in
for the register attributes.
The bit assignments are:
19.5.2.4 Interrupt Set-pending Register
The ISPR forces interrupts into the pending state, and shows which interrupts are
pending. See the register summary in
for the register attributes.
The bit assignments are:
Remark:
Writing 1 to the ISPR bit corresponding to:
•
an interrupt that is pending has no effect
Table 215. ISER bit assignments
Bits
Name
Function
[31:0]
SETENA
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 216. ICER bit assignments
Bits
Name
Function
[31:0]
CLRENA
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 217. ISPR bit assignments
Bits
Name
Function
[31:0]
SETPEND
Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.
