UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
18 of 258
NXP Semiconductors
UM10429
Chapter 3: LPC1102 System configuration
3.5.13 System AHB clock divider register
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
3.5.14 System AHB clock control register
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and
the PMU. This clock cannot be disabled.
Table 17.
Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
Bit
Symbol
Value
Description
Reset value
0
ENA
Enable main clock source update
0x0
0
No change
1
Update clock source
31:1
-
-
Reserved
0x00
Table 18.
System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
Bit
Symbol
Description
Reset
value
7:0
DIV
System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0x01
31:8
-
Reserved
0x00
Table 19.
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
Bit
Symbol
Value
Description
Reset
value
0
SYS
Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
1
0
Reserved
1
Enable
1
ROM
Enables clock for ROM.
1
0
Disable
1
Enable
2
RAM
Enables clock for RAM.
1
0
Disable
1
Enable
