UM10429
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
124 of 258
NXP Semiconductors
UM10429
Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
13.7.9 Capture Register (TMR32B1CR0 - address 0x4001 802C)
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
13.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
The External Match Register provides both control and status of the external match pins
CAP32Bn_MAT[3:0].
If the match outputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules (
Section 13.7.13 “Rules for single edge
controlled PWM outputs” on page 128
1
CAP0FE
Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will
cause CR0 to be loaded with the contents of TC.
0
1
Enabled
0
Disabled
2
CAP0I
Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will
generate an interrupt.
0
1
Enabled
0
Disabled
31:3
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 123. Capture Control Register (TMR32B1CCR - address 0x4001 8028) bit description
Bit
Symbol
Value Description
Reset
value
Table 124. Capture registers (TMR32B1CR0, addresses 0x4001 802C) bit description
Bit
Symbol
Description
Reset
value
31:0
CAP
Timer counter capture value.
0
