NXP Semiconductors LPC1102, User Manual

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Chapter 3: LPC1102 System configuration
3.5.25 Start logic reset register 0
Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit
assignment is identical to
Table 28 . The start-up logic uses the input signals to generate a
clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt
for waking up from Deep-sleep mode. Therefore, the start-up logic states must be cleared
before being used.
3.5.26 Start logic status register 0
This register reflects the status of the enabled start signal bits. The bit assignment is
identical to
Table 28 . Each bit (if enabled) reflects the state of the start logic, i.e. whether
or not a wake-up signal has been received for a given pin.
Table 30. Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit
description
Bit Symbol Value Description Reset
value
0 RSRPIO0_0 Start signal reset for start logic input PIO0_0 n/a
0 -
1 Write: reset start signal
7:1 - - Reserved n/a
8 RSRPIO0_8 Start signal reset for start logic input PIO0_8 n/a
0 -
1 Write: reset start signal
9 RSRPIO0_9 Start signal reset for start logic input PIO0_9 n/a
0 -
1 Write: reset start signal
10 RSRPIO0_10 Start signal reset for start logic input PIO0_10 n/a
0 -
1 Write: reset start signal
11 RSRPIO0_11 Start signal reset for start logic input PIO0_11 n/a
0 -
1 Write: reset start signal
12 RSRPIO1_0 Start signal reset for start logic input PIO1_0 n/a
0 -
1 Write: reset start signal
31:13 - - Reserved n/a
Table 31. Start logic status register 0 (STARTSRP0, address 0x4004 820C) bit description
Bit Symbol Value Description Reset
value
0 SRPIO0_0 Start signal status for start logic input 0PIO0_0 n/a
0 No start signal received
1 Start signal pending
7:1 - - Reserved n/a