NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 23 of 258
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Chapter 3: LPC1102 System configuration
3.5.22 System tick counter calibration register
This register determines the value of the SYST_CALIB register (see Table 138 ).
3.5.23 Start logic edge control register 0
The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO
input to produce a falling or rising clock edge, respectively, for the start logic (see
Section 3.9.2 ).
Every bit in the STARTAPRP0 register controls one port input and is connected to one
wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
0, bit 1 to interrupt 1, etc. (see
Table 44 ), up to a total of 13 interrupts.
Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
corresponding PIO pin is used to wake up the chip from Deep-sleep mode.
4 BODRSTENA BOD reset enable 0
0 Disable reset function.
1 Enable reset function.
31:5 - - Reserved 0x00
Table 26. BOD control register (BODCTRL, address 0x4004 8150) bit description
Bit Symbol Value Description Reset
value
Table 27. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit
description
Bit Symbol Value Description Reset
value
25:0 CAL System tick timer calibration value 0x04
31:26 - - Reserved 0x00
Table 28. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit
description
Bit Symbol Value Description Reset
value
0 APRPIO0_0 Edge select for start logic input PIO0_0 0x0
0 Falling edge
1 Rising edge
7:1 - - Reserved 0x0
8 APRPIO0_8 Edge select for start logic input PIO0_8 0x0
0 Falling edge
1 Rising edge
9 APRPIO0_9 Edge select for start logic input PIO0_9 0x0
0 Falling edge
1 Rising edge