UM10429
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User manual
Rev. 1 — 20 October 2010
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6.1 How to read this chapter
This chapter applies to the LPC1102 part.
6.2 Introduction
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
6.3 Features
•
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0
•
Tightly coupled interrupt controller provides low interrupt latency
•
Controls system exceptions and peripheral interrupts
•
The NVIC supports 32 vectored interrupts
•
4 programmable interrupt priority levels with hardware priority level masking
•
Software interrupt generation
6.4 Interrupt sources
lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
See
for the NVIC register bit descriptions.
Interrupts 0 to 12 are connected to a PIO input pin serving as wake-up pin from
Deep-sleep mode; Interrupt 0 to 11 correspond to PIO0_0 to PIO0_11 and interrupt 12
corresponds to PIO1_0; see
.
UM10429
Chapter 6: LPC1102 Interrupt controller
Rev. 1 — 20 October 2010
User manual
Table 44.
Connection of interrupt sources to the Vectored Interrupt Controller
Exception
Number
Vector
Offset
Function
Flag(s)
0
start logic wake-up
interrupt
start logic input PIO0_0.
7:1
-
Reserved
11:8
start logic wake-up
interrupt
start logic input PIO0_11 to PIO0_8
12
start logic wake-up
interrupt
start logic input PIO1_0
13
-
Reserved
14
-
Reserved
