UM10429
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User manual
Rev. 1 — 20 October 2010
95 of 258
NXP Semiconductors
UM10429
Chapter 11: LPC1102 SPI0 with SSP
11.6.5 SPI/SSP Clock Prescale Register
This register controls the factor by which the Prescaler divides the SPI peripheral clock
SPI_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in the
SSPCR0 registers, to determine the bit clock.
Important:
the SSPnCPSR value must be properly initialized, or the SPI controller will not
be able to transmit data correctly.
In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI
peripheral clock selected in
. The content of the SSPnCPSR register is not
relevant.
In master mode, CPSDVSR
min
= 2 or larger (even numbers only).
11.6.6 SPI/SSP Interrupt Mask Set/Clear Register
This register controls whether each of the four possible interrupt conditions in the SPI
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
3
RFF
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
0
4
BSY
Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.
0
31:5
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Table 94:
SPI/SSP Status Register (SSP0SR - address 0x4004 000C) bit description
Bit
Symbol
Description
Reset Value
Table 95:
SPI/SSP Clock Prescale Register (SSP0CPSR - address 0x4004 0010) bit
description
Bit
Symbol
Description
Reset Value
7:0
CPSDVSR This even value between 2 and 254, by which SPI_PCLK is
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
0
31:8
-
Reserved.
-
