NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 82 of 258
NXP Semiconductors
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Chapter 10: LPC1102 Universal Asynchronous Transmitter (UART)
10.5.13 UART Fractional Divider Register (U0FDR - 0x4000 8028)
The UART Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
a. Mode 0 (start bit and LSB are used for auto-baud)
b. Mode 1 (only start bit is used for auto-baud)
Fig 10. Auto-baud a) mode 0 and b) mode 1 waveform
UARTn RX
start bit LSB of 'A' or 'a'
U0ACR start
rate counter
start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
'A' (0x41) or 'a' (0x61)
16 cycles 16 cycles
16xbaud_rate
UARTn RX
start bit LSB of 'A' or 'a'
rate counter
'A' (0x41) or 'a' (0x61)
start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
U1ACR start
16 cycles
16xbaud_rate