UM10429
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User manual
Rev. 1 — 20 October 2010
16 of 258
NXP Semiconductors
UM10429
Chapter 3: LPC1102 System configuration
3.5.8 System reset status register
if another reset signal - for example EXTRST - remains asserted after the POR signal is
negated, then its bit is set to detected.
3.5.9 System PLL clock source select register
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
(see
) must be toggled from LOW to HIGH for the update to take effect.
Remark:
When switching clock sources, both clocks must be running before the clock
source is updated.
Remark:
When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
Table 13.
System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description
Bit
Symbol
Value
Description
Reset
value
0
POR
POR reset status
0x0
0
no POR detected
1
POR detected
1
EXTRST
0x0
0
no RESET event detected
1
RESET detected
2
WDT
Status of the Watchdog reset
0x0
0
no WDT reset detected
1
WDT reset detected
3
BOD
Status of the Brown-out detect reset
0x0
0
no BOD reset detected
1
BOD reset detected
4
SYSRST
Status of the software system reset
0x0
0
no System reset detected
1
System reset detected
31:5
-
-
Reserved
0x00
Table 14.
System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)
bit description
Bit
Symbol
Value
Description
Reset
value
1:0
SEL
System PLL clock source
0x00
0x0
IRC oscillator
0x1
System oscillator
0x2
Reserved
0x3
Reserved
31:2
-
-
Reserved
0x00
