UM10429
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User manual
Rev. 1 — 20 October 2010
217 of 258
NXP Semiconductors
UM10429
Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
REVSH —
converts 16-bit signed big-endian data into 32-bit signed little-endian data or
16-bit signed little-endian data into 32-bit signed big-endian data.
19.4.5.7.3
Restrictions
In these instructions,
Rd
, and
Rn
must only specify R0-R7.
19.4.5.7.4
Condition flags
These instructions do not change the flags.
19.4.5.7.5
Examples
REV
R3, R7
; Reverse byte order of value in R7 and write it to R3
REV16
R0, R0
; Reverse byte order of each 16-bit halfword in R0
REVSH
R0, R5
; Reverse signed halfword
19.4.5.8 SXT and UXT
Sign extend and Zero extend.
19.4.5.8.1
Syntax
SXTB Rd,
Rm
SXTH Rd,
Rm
UXTB Rd,
Rm
UXTH Rd,
Rm
where:
Rd
is the destination register.
Rm
is the register holding the value to be extended.
19.4.5.8.2
Operation
These instructions extract bits from the resulting value:
•
SXTB extracts bits[7:0] and sign extends to 32 bits
•
UXTB extracts bits[7:0] and zero extends to 32 bits
•
SXTH extracts bits[15:0] and sign extends to 32 bits
•
UXTH extracts bits[15:0] and zero extends to 32 bits.
19.4.5.8.3
Restrictions
In these instructions,
Rd
and
Rm
must only specify R0-R7.
19.4.5.8.4
Condition flags
These instructions do not affect the flags.
