UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
67 of 258
NXP Semiconductors
UM10429
Chapter 9: LPC1102 General Purpose I/O (GPIO)
9.4 Functional description
9.4.1 Write/read data operation
In order for software to be able to set GPIO bits without affecting any other pins in a single
write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide
mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA
bits masked by 1 are affected by read and write operations. The masked GPIOnDATA
register can be located anywhere between address offsets 0x0000 to 0x3FFC in the
GPIOn address space. Reading and writing to the GPIOnDATA register at address
0x3FFC sets all masking bits to 1.
Write operation
If the address bit (i+2) associated with the GPIO port bit i (i = 0 to 11) to be written is
HIGH, the value of the GPIODATA register bit i is updated. If the address bit (i+2) is LOW,
the corresponding GPIODATA register bit i is left unchanged.
Table 69.
GPIOnIC register (GPIO0IC, address 0x5000 801C to GPIO3IC, address 0x5003
801C) bit description
Bit
Symbol
Description
Reset
value
Access
11:0
CLR
Selects interrupt on pin x to be cleared (x = 0 to 11). Clears
the interrupt edge detection logic. This register is write-only.
Remark:
The synchronizer between the GPIO and the
NVIC blocks causes a delay of 2 clocks. It is recommended
to add two NOPs after the clear of the interrupt edge
detection logic before the exit of the interrupt service
routine.
0 = No effect.
1 = Clears edge detection logic for pin PIOn_x.
0x00
W
31:12
-
Reserved
-
-
Fig 8.
Masked write operation to the GPIODATA register
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
u
u
u
u
u
u
1
u
u
1
0
u
13
12
11
10
9
8
7
6
5
4
3
2
0
0
ADDRESS[13:2]
address 0x098
data 0xFE4
GPIODATA register
at a 0x098
u = unchanged
