NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 132 of 258
NXP Semiconductors
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Chapter 14: LPC1102 WatchDog Timer (WDT)
14.5 Description
The Watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (T
WDCLK
×
256
×
4)
and the maximum Watchdog interval is (T
WDCLK
×
2
24
×
4) in multiples of (T
WDCLK
×
4).
The Watchdog should be used in the following manner:
1. Set the Watchdog timer constant reload value in WDTC register.
2. Setup the Watchdog timer operating mode in WDMOD register.
3. Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
4. The Watchdog should be fed again before the Watchdog counter underflows to
prevent reset/interrupt.
When the Watchdog is in the reset mode and the counter underflows, the CPU will be
reset, loading the stack pointer and program counter from the vector table as in the case
of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if
the Watchdog has caused the reset condition. The WDTOF flag must be cleared by
software.
14.6 WDT clocking
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see
Figure 3 ).
The WDCLK is used for the watchdog timer counting and is derived from the wdt_clk in
Figure 3 . Several clocks can be used as a clock source for wdt_clk clock: the IRC, the
watchdog oscillator, and the main clock. The clock source is selected in the syscon block
(see
Table 23 ). The WDCLK has its own clock divider ( Section 3.5.20 ), which can also
disable this clock.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
The watchdog oscillator can be powered down in the PDRUNCFG register
(
Section 3.5.34 ) if it is not used. The clock to the watchdog register block (PCLK) can be
disabled in the SYSAHBCLKCTRL register ( Table 19 ) for power savings.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register (see
Table 11 ) before using the watchdog oscillator for the WDT.
14.7 Register description
The Watchdog contains four registers as shown in Table 129 below.