NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 178 of 258
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
[1] Describes access type during program execution in thread mode and Handler mode. Debug access can
differ.
[2] Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.
19.3.1.3.1 General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
19.3.1.3.2 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
•
0 = Main Stack Pointer (MSP). This is the reset value.
•
1 = Process Stack Pointer (PSP).
Fig 36. Processor core register set
Table 192. Core register set summary
Name Type
[1]
Reset value Description
R0-R12 RW Unknown Section 19–19.3.1.3.1
MSP RW See description Section 19–19.3.1.3.2
PSP RW Unknown Section 19–19.3.1.3.2
LR RW Unknown Section 19–19.3.1.3.3
PC RW See description Section 19–19.3.1.3.4
PSR RW Unknown
[2]
Table 19–193
APSR RW Unknown Table 19–194
IPSR RO
0x00000000
Table 195
EPSR RO Unknown
[2]
Table 19–196
PRIMASK RW
0x00000000
Table 19–197
CONTROL RW
0x00000000
Table 19–198
Program Counter
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP PSP
CONTROL
PSR
Link Register
Stack Pointer
General purpose registers
Program Status Register
Control Register
Special registers
PRIMASK Interrupt mask register