UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
90 of 258
11.1 How to read this chapter
The LPC1102 includes one SPI interface.
Remark:
The SPI block includes the full SSP feature set, and all register names use the
SSP prefix.
11.2 Basic configuration
The SPI0 is configured using the following registers:
1. Pins: The SPI pins must be configured in the IOCONFIG register block.
2. Power: In the SYSAHBCLKCTRL register, set bit 11 (
3. Peripheral clock: Enable the SPI0 peripheral clock by writing to the SSP0CLKDIV
register (
4. Reset: Before accessing the SPI block, ensure that the SSP_RST_N bits (bit 0) in the
PRESETCTRL register (
) is set to 1. This de-asserts the reset signal to the SPI
blocks.
Remark:
Care must be taken when using the SPI because the SPI clock SCK and the
serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the
SPI is enabled, the serial wire debugger is no longer available.
11.3 Features
•
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
•
Synchronous Serial Communication.
•
Supports master or slave operation.
•
Eight-frame FIFOs for both transmit and receive.
•
4-bit to 16-bit frame.
11.4 General description
The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
UM10429
Chapter 11: LPC1102 SPI0 with SSP
Rev. 1 — 20 October 2010
User manual
