UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
94 of 258
NXP Semiconductors
UM10429
Chapter 11: LPC1102 SPI0 with SSP
11.6.3 SPI/SSP Data Register
Software can write data to be transmitted to this register and read data that has been
received.
11.6.4 SPI/SSP Status Register
This read-only register reflects the current status of the SPI controller.
2
MS
Master/Slave Mode.This bit can only be written when the
SSE bit is 0.
0
0
The SPI controller acts as a master on the bus, driving the
SCLK, MOSI, and SSEL lines and receiving the MISO line.
1
The SPI controller acts as a slave on the bus, driving MISO
line and receiving SCLK, MOSI, and SSEL lines.
3
SOD
Slave Output Disable. This bit is relevant only in slave
mode (MS = 1). If it is 1, this blocks this SPI controller from
driving the transmit data line (MISO).
0
31:4
-
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
NA
Table 92:
SPI/SSP Control Register 1 (SSP0CR1 - address 0x4004 0004) bit description
Bit
Symbol
Value
Description
Reset
Value
Table 93:
SPI/SSP Data Register (SSP0DR - address 0x4004 0008) bit description
Bit
Symbol
Description
Reset Value
15:0
DATA
Write:
software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SPI controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bit, software must right-justify the data written to this register.
Read:
software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SPI controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bit, the data is right-justified in this
field with higher order bits filled with 0s.
0x0000
31:16 -
Reserved.
-
Table 94:
SPI/SSP Status Register (SSP0SR - address 0x4004 000C) bit description
Bit
Symbol
Description
Reset Value
0
TFE
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
1
1
TNF
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
2
RNE
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
0
