UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
63 of 258
9.1 How to read this chapter
See
for available GPIO pins:
Register bits corresponding to PIOn_m pins which are not available are reserved.
9.2 Introduction
9.2.1 Features
•
GPIO pins can be configured as input or output by software.
•
Each individual port pin can serve as an edge or level-sensitive interrupt request.
•
Interrupts can be configured on single falling or rising edges and on both edges.
•
Level-sensitive interrupt pins can be HIGH or LOW-active.
•
All GPIO pins are inputs by default.
•
Reading and writing of data registers are masked by address bits 13:2.
9.3 Register description
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
UM10429
Chapter 9: LPC1102 General Purpose I/O (GPIO)
Rev. 1 — 20 October 2010
User manual
Table 59.
GPIO configuration
Part
Package
GPIO port 0
GPIO port 1
GPIO
port 2
GPIO
port 3
Total GPIO
pins
LPC1102
WLCSP16 PIO0_0; PIO0_8 to PIO0_11
PIO1_0 to PIO1_3; PIO1_6 to
PIO1_7
-
-
11
Table 60.
Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000)
Name
Access
Address offset
Description
Reset
value
GPIOnDATA
R/W
0x0000 to 0x3FF8
Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
).
n/a
GPIOnDATA
R/W
0x3FFC
Port n data register for pins PIOn_0 to
PIOn_11
n/a
-
- 0x4000
to
0x7FFC
reserved
-
GPIOnDIR
R/W
0x8000
Data direction register for port n
0x00
GPIOnIS
R/W
0x8004
Interrupt sense register for port n
0x00
GPIOnIBE
R/W
0x8008
Interrupt both edges register for port n
0x00
GPIOnIEV
R/W
0x800C
Interrupt event register for port n
0x00
GPIOnIE
R/W
0x8010
Interrupt mask register for port n
0x00
GPIOnRIS
R
0x8014
Raw interrupt status register for port n
0x00
