NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 107 of 258
NXP Semiconductors
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Chapter 12: LPC1102 16-bit counter/timers (CT16B0/1)
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
TMR16B0MR3 R/W 0x024 Match Register 3 (MR3). See MR0 description. 0
- - 0x028 Reserved -
- - 0x02C Reserved -
TMR16B0EMR R/W 0x03C External Match Register (EMR). The EMR controls the match function
and the external match pins CT16B0_MAT[2:0]. 0
- - 0x040 -
0x06C Reserved -
- - 0x070 Reserved -
TMR16B0PWMC R/W 0x074 PWM Control Register (PWMCON). The PWMCON enables PWM mode
for the external match pins CT16B0_MAT[2:0]. 0
Table 101. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000)
…continued
Name Access Address
offset Description Reset
value
[1]
Table 102. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000)
Name Access Address
offset Description Reset
value
[1]
TMR16B1IR R/W 0x000 Interrupt Register (IR). The IR can be written to clear interrupts. The IR
can be read to identify which of five possible interrupt sources are
pending. 0
TMR16B1TCR R/W 0x004 Timer Control Register (TCR). The TCR is used to control the Timer
Counter functions. The Timer Counter can be disabled or reset through
the TCR. 0
TMR16B1TC R/W 0x008 Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR. 0
TMR16B1PR R/W 0x00C Prescale Register (PR). When the Prescale Counter (below) is equal to
this value, the next clock increments the TC and clears the PC. 0
TMR16B1PC R/W 0x010 Prescale Counter (PC). The 16-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface. 0
TMR16B1MCR R/W 0x014 Match Control Register (MCR). The MCR is used to control if an interrupt
is generated and if the TC is reset when a Match occurs. 0
TMR16B1MR0 R/W 0x018 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC. 0
TMR16B1MR1 R/W 0x01C Match Register 1 (MR1). See MR0 description. 0
TMR16B1MR2 R/W 0x020 Match Register 2 (MR2). See MR0 description. 0
TMR16B1MR3 R/W 0x024 Match Register 3 (MR3). See MR0 description. 0
- - 0x028 Reserved -
- - 0x02C Reserved -
TMR16B1EMR R/W 0x03C External Match Register (EMR). The EMR controls the match function
and the external match pins CT16B1_MAT[1:0]. 0