UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
91 of 258
NXP Semiconductors
UM10429
Chapter 11: LPC1102 SPI0 with SSP
11.5 Pin description
Remark:
Care must be taken when using the SPI because the SPI clock SCK and the
serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the
SPI is enabled, the serial wire debugger is no longer available.
11.6 Register description
The register addresses of the SPI controllers are shown in
.
Table 89.
SPI pin descriptions
Pin
name
Type
Interface pin
name/function
Pin description
SPI
SSI
Microwire
SCK0/1
I/O
SCK
CLK
SK
Serial Clock.
SCK/CLK/SK is a clock signal used
to synchronize the transfer of data. It is driven by
the master and received by the slave. When
SPI/SSP interface is used, the clock is
programmable to be active-high or active-low,
otherwise it is always active-high. SCK only
switches during a data transfer. Any other time, the
SPI/SSP interface either holds it in its inactive state
or does not drive it (leaves it in high-impedance
state).
SSEL0
I/O
SSEL FS
CS
Frame Sync/Slave Select.
When the SPI/SSP
interface is a bus master, it drives this signal to an
active state before the start of serial data and then
releases it to an inactive state after the data has
been sent.The active state of this signal can be
high or low depending upon the selected bus and
mode. When the SPI/SSP interface is a bus slave,
this signal qualifies the presence of data from the
Master according to the protocol in use.
When there is just one bus master and one bus
slave, the Frame Sync or Slave Select signal from
the Master can be connected directly to the slave’s
corresponding input. When there is more than one
slave on the bus, further qualification of their Frame
Select/Slave Select inputs will typically be
necessary to prevent more than one slave from
responding to a transfer.
MISO0
I/O
MISO DR(M)
DX(S)
SI(M)
SO(S)
Master In Slave Out.
The MISO signal transfers
serial data from the slave to the master. When the
SPI/SSP is a slave, serial data is output on this
signal. When the SPI/SSP is a master, it clocks in
serial data from this signal. When the SPI/SSP is a
slave and is not selected by FS/SSEL, it does not
drive this signal (leaves it in high-impedance state).
MOSI0
I/O
MOSI DX(M)
DR(S)
SO(M)
SI(S)
Master Out Slave In.
The MOSI signal transfers
serial data from the master to the slave. When the
SPI/SSP is a master, it outputs serial data on this
signal. When the SPI/SSP is a slave, it clocks in
serial data from this signal.
