NR Electric PCS-9611, Instruction Manual, Page: 41 / 300

3 Operation Theory
PCS-9611 Feeder Relay
3-5
Date: 2014-04-08
relevant settings can enable or disable the corresponding protection.
The stage 1, 2, 5 and 6 overcurrent protections only have definite time characteristics. The stage
3 and 4 overcurrent protections can be set as either definite time (DT) or inverse definite minimum
time (IDMT). If the settings [50/51P3.Opt_Curve] and [50/51P4.Opt_Curve] are set as
“0”, the
stage 3 and 4 overcurrent protections can be with definite time characteristics.
The demonstration characteristic figure of the DT overcurrent protection and IDMT overcurrent
protection is shown as below.
t
Delay
50/51P2.I_Set
I
nom
50/51P1.I_Set
50/51P2.t_Op
50/51P1.t_Op
t
Delay
I
nom
DT OC IDMT OC
Figure 3.3-1 Demonstration characteristic of the overcurrent protection
The logic diagram of the stage 1 overcurrent protection is shown in Figure 3.3-2 . The overcurrent
block is a level detector that detects whether the current magnitude is above the threshold.
[50/51P1.Op]
[50/51P1.St]
[50/51P1.En1]
[50/51P1.En]
[50/51P1.Blk]
&
Ia > [50/51P1.I_Set]
&
50/51P1.Dir_A
50/51P1.VCE_A
50/51P1.HmBlk_A
Ib > [50/51P1.I_Set]
&
50/51P1.Dir_B
50/51P1.VCE_B
50/51P1.HmBlk_B
Ic > [50/51P1.I_Set]
&
50/51P1.Dir_C
50/51P1.VCE_C
50/51P1.HmBlk_C
t
OC1
0
Figure 3.3-2 Logic diagram of the stage 1 overcurrent protection
Where:
[50/51P1.I_Set] is the current setting of the stage 1 overcurrent protection;
“t
OC1
” is the setting [50/51P1.t_Op], the time setting of the stage 1 overcurrent protection;
[50/51P1.En] is the logic setting of the stage 1 overcurrent protection;
[50/51P1.En1] is the binary signal for enabling the stage 1 overcurrent protection;
[50/51P1.Blk] is the binary signal for blocking the stage 1 overcurrent protection;