NR Electric PCS-9611, Instruction Manual

Page: 159 / 300

7 Settings
PCS-9611 Feeder Relay
7-15
Date: 2014-04-08
3 50BC.En
The logic setting for the broken conductor
protection
0~1 1
4 50BC.OutMap
The output matrix setting of the broken conductor
protection
0x00000 ~
0xFFFFF
1
7.3.7 Cold Load Pickup Settings
The cold load pickup logic settings (in the submenu
“
CLP Settings
”) are used to determine the
characteristic of the cold load pickup logic.
All the settings of the cold load pickup logic are listed in the following table
No. Menu text Explanation Range Step
1 CLP.Opt_LogicMode The setting for selecting the cold load condition 1~2 1
2 CLP.t_Cold
The time setting for ensuring the cold load
condition is met
0~4000s 0.001s
3 CLP.t_Rst
The time setting for resetting the cold load pickup
logic
0~4000s 0.001s
4 CLP.t_ShortRst
The time setting for fast resetting the cold load
pickup logic
0~600s 0.001s
5 CLP.En
The logic setting of the cold load pickup logic
function
0~1 1
6 50/51P1.CLP.IMult
The multiple setting of the stage 1 overcurrent
protection when CLP is active
1.00~10.00 0.001
7 50/51P1.CLP.t_Op
The time s etting of the stage 1 overcurrent
protection when CLP is active
0~100s 0.001s
8 50/51P2.CLP.IMult
The multiple setting of the stage 2 overcurrent
protection when CLP is active
1.00~10.00 0.001
9 50/51P2.CLP.t_Op
The time s etting of the stage 2 overcurrent
protection when CLP is active
0~100s 0.001s
10 50/51P3.CLP.IMult
The multiple setting of the stage 3 overcurrent
protection when CLP is active
1.00~10.00 0.001
11 50/51P3.CLP.t_Op
The time s etting of the stage 3 overcurrent
protection when CLP is active
0~100s 0.001s
12 50/51P4.CLP.IMult
The multiple setting of the stage 4 overcurrent
protection when CLP is active
1.00~10.00 0.001
13 50/51P4.CLP.t_Op
The time s etting of the stage 4 overcurrent
protection when CLP is active
0~100s 0.001s
14 50/51P4.CLP.TMS
The time multiplier setting of the IDMT overcurrent
protection when CLP is active
0.05~100.0 0.001
15 50/51G1.CLP.IMult
The multiple setting of the stage 1 zero sequence
overcurrent protection when CLP is active
1.00~10.00 0.001
16 50/51G1.CLP.t_Op
The time s etting of the stage 1 zero sequence
overcurrent protection when CLP is active
0~100s 0.001s