CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
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(6) Wait signal (WAIT)
The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing
to transmit or receive data (i.e., is in a wait state).
Setting the SCL pin to low level notifies the communication partner of the wait status. When the wait status
has been canceled for both the master and slave devices, the next data transfer can begin.
Figure 12-31. Wait Signal (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(Master: transmission, slave: reception, and ACKE = 1)
SCL
6
SDA
7
8
9
1
2
3
SCL
IIC
6
H
7
8
1
2
3
D2
D1
D0
ACK
D7
D6
D5
9
IIC
SCL
ACKE
Master
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of ninth clock.
IIC data write (cancel wait)
Slave
Wait after output
of eighth clock.
FFH is written to IIC or WREL is set to 1.
Transfer lines
Summary of Contents for V850ES/SA2 UPD703201
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