CHAPTER 4 PORT FUNCTIONS
Preliminary User’s Manual U15905EJ1V0UD
103
Figure 4-4. Block Diagram of P01 to P04
Internal bus
WR
PMC
RD
Address
INTP0 to INTP3 input
TI2 to TI5 input
WR
PORT
P01/INTP0/TI2,
P02/INTP1/TI3,
P03/INTP2/TI4,
P04/INTP3/TI5
PMC0n
WR
INTF
INTF0n
Selector
Selector
WR
PU
PU0n
WR
PM
PM0n
P0n
Noise elimination,
edge detection
Noise elimination,
edge detection
WR
INTR
INTR0n
PMC0
INTF0
PU0
PM0
P0
INTR0
EV
DD
P-ch
Remarks 1.
P0:
Port
register
0
PM0: Port mode register 0
PMC0: Port mode control register 0
PU0:
Pull-up resistor option register 0
INTR0: External interrupt rising edge specification register 0
INTF0: External interrupt falling edge specification register 0
2.
n = 1 to 4
Summary of Contents for V850ES/SA2 UPD703201
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