CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
388
Table 12-9. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
Interrupt Request Generation Timing
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK signal transfer period after data transmission
When restart condition is detected during data transfer
At falling edge of eighth or ninth clock following
byte transfer
Note 1
When stop condition is detected during data transfer
When stop condition is output (when SPIE = 1)
Note 2
When data is at low level while attempting to output a restart condition
At falling edge of eighth or ninth clock following
byte transfer
Note 1
When stop condition is detected while attempting to output a restart condition
When stop condition is output (when SPIE = 1)
Note 2
When data is at low level while attempting to output a stop condition
When SCL is at low level while attempting to output a restart condition
At falling edge of eighth or ninth clock following
byte transfer
Note 1
Notes 1.
When WTIM (bit 3 of IIC control register (IICC)) = 1, an interrupt request occurs at the falling edge of the
ninth clock. When WTIM = 0 and the extension code’s slave address is received, an interrupt request
occurs at the falling edge of the eighth clock.
2.
When there is a possibility that arbitration will occur, set SPIE = 1 for master device operation.
Remark
SPIE: Bit 5 of IIC control register (IICC)
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