CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
353
(2) IIC status register (IICS)
The IICS register is used to indicate the status of I
2
C.
The IICS register can be set by an 8-bit or 1-bit memory manipulation instruction. IICS is a read-only register.
RESET input clears the IICS register to 00H.
(1/3)
MSTS
Condition for clearing (MSTS = 0)
•
When a stop condition is detected
•
When ALD = 1
•
Cleared by LREL = 1
•
When IICE changes from 1 to 0
•
When RESET is input
Condition for setting (MSTS = 1)
•
When a start condition is generated
MSTS
0
1
Slave device status or communication standby status
Master device communication status
Master device status
IICS
ALD
EXC
COI
TRC
ACKD
STD
SPD
After reset:
00H R
Address:
FFFFFD86H
Condition for clearing (ALD = 0)
•
Automatically cleared after IICS is read
Note
•
When IICE changes from 1 to 0
•
When RESET is input
Condition for setting (ALD = 1)
•
When the arbitration result is a “loss”.
ALD
0
1
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. MSTS is cleared.
Detection of arbitration loss
Condition for clearing (EXC = 0)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by LREL = 1
•
When IICE changes from 1 to 0
•
When RESET is input
EXC
0
1
Extension code was not received.
Extension code was received.
Detection of extension code reception
Condition for setting (EXC = 1)
•
When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising
edge of the eighth clock).
Note
This register is also cleared when a bit manipulation instruction is executed for bits other than IICS.
Remark
LREL: Bit 6 of IIC control register (IICC)
IICE:
Bit 7 of IIC control register (IICC)
Summary of Contents for V850ES/SA2 UPD703201
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