CHAPTER 6 CLOCK GENERATION FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
206
6.2
Configuration
Figure 6-1. Clock Generator
FRC bit
MFRC bit
CK3 to CK0 bits
STOP mode
Subclock
oscillator
Port CM
WDT clock
control
Prescaler 1
Prescaler 2
IDLE
control
IDLE
control
HALT
control
HALT mode
CPU clock
A/
D converter
RTC clock
Peripheral clock
WDT clock
Internal system
clock
Prescaler 3
Main clock
oscillator
Main clock
oscillator
stop control
XT1
XT2
CLKOUT
X1
X2
IDLE
Selector
f
X
/32
f
X
/16
f
X
/8
f
X
/4
f
X
/2
f
X
f
CPU
f
XX
/f
XT
f
XT
f
X
-f
X
/512
f
X
/2
6
to f
X
/2
9
f
XT
f
XT
f
X
f
X
f
XW
Remark
f
X
: Main
clock
frequency
f
XT
: Subclock
frequency
f
CPU
: CPU clock frequency
f
XX
:
Internal system clock frequency
f
XW
: Watchdog timer clock frequency
Summary of Contents for V850ES/SA2 UPD703201
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