CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
360
12.4.4 I
2
C bus definitions and control methods
The following section describes the I
2
C bus’s serial data communication format and the signals used by the I
2
C bus.
The transfer timing for the “start condition”, “data”, and “stop condition” output via the I
2
C bus’s serial data bus is
shown below.
Figure 12-25. I
2
C Bus Serial Data Transfer Timing
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SCL
SDA
Start
condition
Address
R/W
ACK
Data
Data
Stop
condition
ACK
ACK
The master device outputs the start condition, slave address, and stop condition.
The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL) is continuously output by the master device. However, in the slave device, SCL’s low-level
period can be extended and a wait can be inserted.
(1) Start condition
A start condition is met when the SCL pin is at high level and the SDA pin changes from high level to low level.
The start conditions for the SCL pin and SDA pin are signals that the master device outputs to the slave device
when starting a serial transfer. The slave device includes hardware for detecting start conditions.
Figure 12-26. Start Conditions
H
SCL
SDA
A start condition is output when bit 1 (STT) of the IIC control register (IICC) is set to 1 after a stop condition
has been detected (SPD: Bit 0 = 1 in IIC status register (IICS)). When a start condition is detected, bit 1 (STD)
of IICS is set to 1.
Summary of Contents for V850ES/SA2 UPD703201
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