CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U15905EJ1V0UD
49
(9) PCM0 to PCM3 (Port CM) (V850ES/SA2) … 3-state I/O
PCM0 to PCM5 (Port CM) (V850ES/SA3) … 3 state I/O
[V850ES/SA2]
Port CM is a 4-bit I/O port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, in the control mode PCM0 to PCM3 also operate as the bus hold control
signal output and bus clock output pins, and as the control signal that inserts a wait state (WAIT) in the bus
cycle.
(a) Port mode
PCM0 to PCM3 can be set to the input or output mode in 1-bit units by using port mode register CM
(PMCM).
(b) Control mode
(i) HLDAK (hold acknowledge) … Output
This pin outputs an acknowledge signal indicating that the V850ES/SA2 has made the address bus,
data bus, and control bus go into a high-impedance state, in response to a bus hold request.
While this signal is active, the address bus, data bus, and control bus are in the high-impedance state.
(ii) HLDRQ (hold request) … Input
This pin is used by an external device to request the V850ES/SA2 to release the address bus, data
bus, and control bus. A signal can be input to this pin asynchronously to CLKOUT. When this pin is
active, the V850ES/SA2 makes the address bus, data bus, and control bus go into a high-impedance
state immediately or after completion of the bus cycle under execution, if any, and then asserts the
HLDAK signal and releases the bus.
(iii) CLKOUT (clock output) … Output
This pin outputs the internally generated bus clock.
(iv) WAIT (wait) … Input
This pin inputs a control signal that inserts a wait state in the bus cycle. It is sampled at the falling
edge of the clock in the T2 and TW states of the bus cycle.
The wait function is turned ON/OFF by port mode control register CM (PMCCM).
Summary of Contents for V850ES/SA2 UPD703201
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