Preliminary User’s Manual U15905EJ1V0UD
17
LIST OF FIGURES (3/5)
Figure No.
Title
Page
7-19
Timing of External Event Counter Operation (with Rising Edge Specified)................................................... 252
7-20
Timing of Square-Wave Output Operation .................................................................................................... 254
7-21
Timing of PWM Output Operation ................................................................................................................. 256
7-22
Timing of Operation Based on CRn Register Transitions ............................................................................. 257
7-23
Cascade Connection Mode with 16-Bit Resolution (When TM2 and TM3 Are Connected) .......................... 259
7-24
Start Timing of Timer n.................................................................................................................................. 262
8-1
Block Diagram of Real-Time Counter............................................................................................................ 263
9-1
Block Diagram of Watchdog Timer................................................................................................................ 274
10-1
Block Diagram of A/D Converter ................................................................................................................... 281
10-2
Block Diagram of Power Fail Detection Function .......................................................................................... 282
10-3
Power Fail Monitoring Function (PFCM = 0) ................................................................................................. 290
11-1
Block Diagram of D/A Converter ................................................................................................................... 291
11-2
External Pin Connection Example................................................................................................................. 295
12-1
Selecting CSI1 or UART0 Mode.................................................................................................................... 297
12-2
Selecting CSI0 or I
2
C Mode........................................................................................................................... 298
12-3
Asynchronous Serial Interface n Block Diagram ........................................................................................... 301
12-4
Asynchronous Serial Interface Transmit/Receive Data Format .................................................................... 310
12-5
Asynchronous Serial Interface Transmission Completion Interrupt Timing................................................... 312
12-6
Continuous Transmission Processing Flow .................................................................................................. 314
12-7
Continuous Transmission Starting Procedure............................................................................................... 315
12-8
Continuous Transmission End Procedure..................................................................................................... 316
12-9
Asynchronous Serial Interface Reception Completion Interrupt Timing........................................................ 318
12-10
When Reception Error Interrupt Is Separated from
Reception Completion Interrupt (INTSRn) (ISRMn Bit = 0) ........................................................................... 319
12-11
When Reception Error Interrupt Is Included in
Reception Completion Interrupt (INTSRn) (ISRMn Bit = 1) ........................................................................... 319
12-12
Noise Filter Circuit ......................................................................................................................................... 321
12-13
Timing of RXDn Signal Judged as Noise ...................................................................................................... 321
12-14
Configuration of Baud Rate Generator n (BRGn).......................................................................................... 322
12-15
Allowable Baud Rate Range During Reception............................................................................................. 327
12-16
Transfer Rate During Continuous Transmission ........................................................................................... 329
12-17
Clocked Serial Interface Block Diagram........................................................................................................ 331
12-18
Transfer Timing ............................................................................................................................................. 339
12-19
Clock Timing.................................................................................................................................................. 340
12-20
System Configuration Example of CSI .......................................................................................................... 342
Summary of Contents for V850ES/SA2 UPD703201
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