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NEC V850ES/SA2 UPD703201, Manual

The NEC V850ES/SA2 UPD703201 is a powerful product designed to meet your needs. Our user manual, available for free download on manualshive.com, provides detailed instructions and information for utilizing the product's features to their fullest potential. Get the most out of your device with our comprehensive user manual.

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CHAPTER  13   DMA FUNCTIONS (DMA CONTROLLER)

Preliminary User’s Manual  U15905EJ1V0UD

411

Table 13-1.  DMA Start Factor

IFCn5

IFCn4

IFCn3

IFCn2

IFCn1

IFCn0

Interrupt Source

0

0

0

0

0

0

DMA request by interrupt disabled

0

0

0

0

0

1

INTWDTM

0

0

0

0

1

0

INTP0

0

0

0

0

1

1

INTP1

0

0

0

1

0

0

INTP2

0

0

0

1

0

1

INTP3

0

0

0

1

1

0

INTP4

0

0

0

1

1

1

INTP5

0

0

1

0

0

0

INTP6

0

0

1

0

0

1

INTRTC

0

0

1

0

1

0

INTCC00

0

0

1

0

1

1

INTCC01

0

0

1

1

0

0

INTOVF0

0

0

1

1

0

1

INTCC10

0

0

1

1

1

0

INTCC11

0

0

1

1

1

1

INTOVF1

0

1

0

0

0

0

INTTM2

0

1

0

0

0

1

INTTM3

0

1

0

0

1

0

INTTM4

0

1

0

0

1

1

INTTM5

0

1

0

1

0

0

INTCSI0

0

1

0

1

0

1

INTIIC

0

1

0

1

1

0

INTCSI1

0

1

0

1

1

1

INTSRE0

0

1

1

0

0

0

INTSR0

0

1

1

0

0

1

INTST0

0

1

1

0

1

0

INTCSI2

0

1

1

0

1

1

INTSRE1

0

1

1

1

0

0

INTSR1

0

1

1

1

0

1

INTST1

0

1

1

1

1

0

INTCSI3

0

1

1

1

1

1

INTCSI4

1

0

0

0

0

0

INTAD

1

0

0

0

0

1

INTOVF

1

0

0

0

1

0

INTBRG

1

0

0

1

1

1

Setting prohibited after this

Remark

n = 0 to 3

Summary of Contents for V850ES/SA2 UPD703201

Page 1: ...ocontrollers Hardware Document No U15905EJ1V0UD00 1st edition Date Published March 2002 N CP K Printed in Japan 2001 V850ES SA2 V850ES SA3 µ µ µ µPD703201 µ µ µ µPD703204 µ µ µ µPD703201Y µ µ µ µPD703204Y µ µ µ µPD70F3201 µ µ µ µPD70F3204 µ µ µ µPD70F3201Y µ µ µ µPD70F3204Y 2002 ...

Page 2: ...Preliminary User s Manual U15905EJ1V0UD 2 MEMO ...

Page 3: ...e input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an outpu...

Page 4: ...rposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While N...

Page 5: ...588 6130 800 729 9288 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Br...

Page 6: ...nctions Data types CPU function Register set On chip peripheral functions Instruction format and instruction set Flash memory programming Interrupts and exceptions Electrical specifications target Pipeline operation How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers To understand t...

Page 7: ...versions are not marked as such Documents related to V850ES SA2 and V850ES SA3 Document Name Document No V850ES Architecture User s Manual U15943E V850ES SA2 and V850ES SA3 Hardware User s Manual This manual Documents related to development tools Document Name Document No IE V850ES G1 In Circuit Emulator To be prepared IE 703204 G1 EM1 In Circuit Emulator Option Board To be prepared Operation U150...

Page 8: ...f Pin I O Circuits I O Buffer Power Supplies and Connection of Unused Pins 56 CHAPTER 3 CPU FUNCTION 60 3 1 Features 60 3 2 CPU Register Set 61 3 2 1 Program register set 62 3 2 2 System register set 63 3 3 Operation Modes 69 3 3 1 Operation modes 69 3 4 Address Space 70 3 4 1 CPU address space 70 3 4 2 Image 71 3 4 3 Wrap around of CPU address space 72 3 4 4 Memory map 73 3 4 5 Areas 75 3 4 6 Rec...

Page 9: ...I O is accessed 182 5 2 2 Pin status in each operation mode 182 5 3 Memory Block Function 183 5 3 1 Chip select control function 184 5 4 External Bus Interface Mode Control Function 184 5 5 Bus Access 185 5 5 1 Number of clocks for access 185 5 5 2 Bus size setting function 185 5 5 3 Access by bus size 186 5 6 Wait Function 192 5 6 1 Programmable wait function 192 5 6 2 External wait function 193 ...

Page 10: ...mer Event Counters 2 to 5 TM2 to TM5 243 7 2 1 Function outline 243 7 2 2 Configuration of 8 bit timer event counter n 244 7 2 3 Registers controlling 8 bit timer event counters 2 to 5 246 7 3 Operation of 8 Bit Timer Event Counters 2 to 5 250 7 3 1 Operation as interval timer 8 bits 250 7 3 2 Operation as external event counter 8 bits 252 7 3 3 Square wave output operation 8 bit resolution 253 7 ...

Page 11: ...2 11 3 D A Converter Control Registers 292 11 4 Operation 294 11 4 1 Operation in normal mode 294 11 4 2 Operation in real time output mode 294 11 4 3 Cautions 295 CHAPTER 12 SERIAL INTERFACE FUNCTION 296 12 1 Features 296 12 1 1 Selecting CSI1 or UART0 mode 297 12 1 2 Selecting CSI0 or I 2 C mode 298 12 2 Asynchronous Serial Interface n UARTn 299 12 2 1 Features 299 12 2 2 Configuration 300 12 2 ...

Page 12: ...2 DMA destination address registers 0 to 3 DDA0 to DDA3 406 13 3 3 DMA byte count registers 0 to 3 DBC0 to DBC3 407 13 3 4 DMA addressing control registers 0 to 3 DADC0 to DADC3 408 13 3 5 DMA channel control registers 0 to 3 DCHC0 to DCHC3 409 13 3 6 DMA trigger factor registers 0 to 3 DTFR0 to DTFR3 410 13 4 DMA Bus States 412 13 4 1 Types of bus states 412 13 4 2 DMAC bus cycle state transition...

Page 13: ...441 14 4 2 Restore 442 14 4 3 Exception status flag EP 443 14 5 Exception Trap 444 14 5 1 Illegal opcode definition 444 14 6 Interrupt Acknowledge Time of CPU 446 14 7 Periods in Which Interrupts Are Not Acknowledged by CPU 447 CHAPTER 15 STANDBY FUNCTION 448 15 1 Overview 448 15 2 HALT Mode 451 15 2 1 Setting and operation status 451 15 2 2 Releasing HALT mode 451 15 3 IDLE Mode 453 15 3 1 Settin...

Page 14: ...PTER 18 FLASH MEMORY 475 18 1 Features 475 18 1 1 Erasure unit 476 18 2 Writing with Flash Programmer 477 18 3 Programming Environment 477 18 4 Communication Mode 478 18 5 Pin Connection 480 18 5 1 FLMD0 pin 480 18 5 2 Serial interface pin 480 18 5 3 RESET pin 483 18 5 4 Port pins including NMI 483 18 5 5 Other signal pins 483 18 5 6 Power supply 483 18 6 Programming Method 484 18 6 1 Flash memory...

Page 15: ... P31 116 4 10 Block Diagram of P32 117 4 11 Block Diagram of P40 123 4 12 Block Diagram of P41 124 4 13 Block Diagram of P42 125 4 14 Block Diagram of P43 and P45 126 4 15 Block Diagram of P44 and P46 127 4 16 Block Diagram of P70 to P715 129 4 17 Block Diagram of P80 and P81 131 4 18 Block Diagram of P90 and P91 141 4 19 Block Diagram of P92 and P93 142 4 20 Block Diagram of P94 to P97 and P99 14...

Page 16: ...ss 204 6 1 Clock Generator 206 6 2 Block Diagram of Prescaler 3 212 7 1 Block Diagram of 16 Bit Timer Event Counter 216 7 2 Basic Operation of 16 Bit Timer Event Counter 226 7 3 Operation After Overflow When OSTn 1 227 7 4 Capture Operation Example TM1 228 7 5 TM1 Capture Operation Example When Both Edges Are Specified 229 7 6 Compare Operation Example When CCLR1 1 and CC10 Is Other Than 0000H 230...

Page 17: ... Asynchronous Serial Interface n Block Diagram 301 12 4 Asynchronous Serial Interface Transmit Receive Data Format 310 12 5 Asynchronous Serial Interface Transmission Completion Interrupt Timing 312 12 6 Continuous Transmission Processing Flow 314 12 7 Continuous Transmission Starting Procedure 315 12 8 Continuous Transmission End Procedure 316 12 9 Asynchronous Serial Interface Reception Completi...

Page 18: ...ion When 9 Clock Wait Is Selected for Both Master and Slave 397 12 39 Example of Slave to Master Communication When 9 Clock Wait Is Selected for Both Master and Slave 400 13 1 DMAC Bus Cycle Two Cycle Transfer State Transition 413 14 1 Non Maskable Interrupt Request Acknowledgement Operation 421 14 2 Servicing Configuration of Non Maskable Interrupt 423 14 3 RETI Instruction Processing 424 14 4 Ma...

Page 19: ...Operation and Program Flow 474 18 1 Environment Required for Writing Programs to Flash Memory 477 18 2 Communication with Dedicated Flash Programmer UART0 478 18 3 Communication with Dedicated Flash Programmer CSI0 478 18 4 Communication with Dedicated Flash Programmer CSI0 HS 479 18 5 FLMD0 Pin Connection Example 480 18 6 Conflict of Signals Serial Interface Input Pin 481 18 7 Malfunction of Othe...

Page 20: ... of Port 4 118 4 8 Alternate Function Pins of Port 7 128 4 9 Alternate Function Pins of Port 8 130 4 10 Alternate Function Pins of Port 9 132 4 11 Specifying Valid Edge 140 4 12 Alternate Function Pins of Port CD V850ES SA3 147 4 13 Alternate Function Pins of Port CM 150 4 14 Alternate Function Pins of Port CS 156 4 15 Alternate Function Pins of Port CT 161 4 16 Alternate Function Pins of Port DH ...

Page 21: ...nal Generation Timing and Wait Control 385 12 8 Extension Code Bit Definitions 386 12 9 Status During Arbitration and Interrupt Request Generation Timing 388 12 10 Wait Periods 390 13 1 DMA Start Factor 411 13 2 Relationship Between Transfer Type and Transfer Object 415 13 3 External Bus Cycles During DMA Transfer Two Cycle Transfer 415 14 1 Interrupt Exception Source List 419 14 2 Specifying Vali...

Page 22: ... Sub IDLE Mode 461 15 11 Operation Status in Backup Mode 465 16 1 Hardware Status on RESET Pin Input 469 16 2 Hardware Status on Occurrence of WDTRES 469 17 1 Correspondence Between CORCN Register Bits and CORADn Registers 473 18 1 Signal Generation of Dedicated Flash Programmer PG FP4 479 18 2 Pins Used by Serial Interfaces 480 18 3 List of Communication Modes 486 18 4 Flash Memory Control Comman...

Page 23: ...deal for digital servo control applications such as multiplication instructions using a hardware multiplier saturated operation instructions and bit manipulation instructions as well as basic instructions with a short real time response speed and a 1 clock pitch These microcontrollers can be used in real time control systems requiring low power consumption such as DVC and portable audio systems wi...

Page 24: ...sertion function External bus interface Separate bus multiplexed bus output selectable 8 16 bit data bus sizing function 4 space chip select function Wait functions Programmable wait function External wait function Idle state function Bus hold function Internal memory RAM 16 KB Mask ROM 256 KB µPD703201 703201Y 703204 703204Y Flash memory 256 KB µPD70F3201 70F3201Y 70F3204 70F3204Y Interrupts exce...

Page 25: ...nverter 10 bit resolution 12 ch V850ES SA2 16 ch V850ES SA3 D A converter 8 bit resolution 2 ch DMA controller 4 ch ROM correction 4 places specifiable Clock generator Main clock subclock operation CPU clock 7 steps fX fX 2 fX 4 fX 8 fX 16 fX 32 fXT Power save function HALT IDLE STOP and backup mode Package 100 pin plastic TQFP fine pitch 14 14 V850ES SA2 121 pin plastic FBGA 12 12 V850ES SA3 1 3 ...

Page 26: ...4 14 Flash memory 256 KB µPD70F3201YGC YEU 100 pin plastic TQFP fine pitch 14 14 Flash memory 256 KB Remarks 1 indicates ROM code suffix 2 No ROMless model is available 1 4 2 V850ES SA3 Part Number Package Internal ROM µPD703204F1 EA6 121 pin plastic FBGA 12 12 Mask ROM 256 KB µPD703204YF1 EA6 121 pin plastic FBGA 12 12 Mask ROM 256 KB µPD70F3204F1 EA6 121 pin plastic FBGA 12 12 Flash memory 256 K...

Page 27: ... A10 SI2 P911 A11 SO2 P912 A12 SCK2 P913 A13 SI3 P914 A14 SO3 P915 A15 SCK3 EV SS EV DD PCS0 CS0 PCS1 CS1 PCS2 CS2 PCS3 CS3 PCM0 WAIT PCM1 CLKOUT PCM2 HLDAK PCM3 HLDRQ PCT0 WR0 PCT1 WR1 PCT4 RD PCT5 PCT6 ASTB 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AVREF0 AVDD AVSS P80 ANO0 P81 ANO1 AVREF1 P00 NMI P30 SI1 RXD0 P31 SO1 TXD0 P32 SCK1 VDD VSS X1 X2 RESET XT1 XT2 VSS...

Page 28: ... PDH1 A17 A6 P78 ANI8 B13 PDH4 A20 E1 P30 SI1 RXD0 A7 P711 ANI11 C1 P80 ANO0 E2 P31 SO1 TXD0 A8 P04 INTP3 TI5 C2 AVSS E3 P32 SCK1 A9 PCD2 C3 P74 ANI4 E11 PDL14 AD14 A10 P45 INTP10 TI1 TCLR1 C4 P714 ANI14 E12 PDH6 A22 A11 P43 INTP00 TI0 TCLR0 C5 P715 ANI15 E13 PDL15 AD15 A12 P41 SO0 SDANote C6 P79 ANI9 F1 VSS A13 PDH5 A21 C7 P05 INTP4 F2 X1 B1 AVDD C8 P03 INTP2 TI4 F3 VDD B2 AVREF0 C9 PCD1 F11 PDL1...

Page 29: ...8 A8 RXD1 J1 P20 SI4 L9 PCM4 N3 P910 A10 SI2 J2 P91 A1 L10 PCT2 N4 P912 A12 SCK2 J3 P90 A0 L11 PCT0 WR0 N5 PCS7 J11 PDL5 AD5 FLMD1Note 1 L12 PDL1 AD1 N6 PCS6 J12 PDL7 AD7 L13 PDL2 AD2 N7 PCS1 CS1 J13 PDL6 AD6 M1 P95 A5 TO3 N8 PCS3 CS3 K1 P22 SCK4 M2 P97 A7 TO5 N9 PCM5 K2 P92 A2 INTP5 M3 P99 A9 TXD1 N10 PCM3 HLDRQ K3 P21 SO4 M4 P913 A13 SI3 N11 PCT1 WR1 K11 PCM1 CLKOUT M5 EVSS N12 PCT5 K12 PDL4 AD4...

Page 30: ...dge Hold request Internally connected Interrupt request from peripherals Interrupt request to timer Non maskable interrupt request Port 0 Port 2 Port 3 Port 4 Port 7 Port 8 Port 9 PCD1 to PCD3 PCM0 to PCM5 PCS0 to PCS7 PCT0 to PCT7 PDH0 to PDH7 PDL0 to PDL15 RD RESET RXD0 RXD1 SCK0 to SCK4 SCL SDA SI0 to SI4 SO0 to SO4 TCLR0 TCLR1 TI0 to TI5 TO0 to TO5 TXD0 TXD1 VDD VDDBU VSS VSSBU WAIT WR0 WR1 X1...

Page 31: ...isters 32 bits 32 Multiplier 16 16 32 ALU System registers 32 bit barrel shifter CPU HLDRQ HLDAK ASTB RD WAIT WR0 WR1 CS0 to CS3 A0 to A21 AD0 to AD15 ICNote 3 FLMD0Note 4 FLMD1Note 4 Port CG RG A D converter D A converter PCS0 to PCS3 PCM0 to PCM3 PCT0 PCT1 PCT4 to PCT7 PDH0 to PDH5 PDL0 to PDL15 P90 to P915 P80 P81 P70 to P711 P40 to P46 P30 to P32 P00 to P05 ANO0 ANO1 AV REF1 AV DD AV REF0 AV S...

Page 32: ...ALU System registers 32 bit barrel shifter CPU HLDRQ HLDAK ASTB RD WAIT WR0 WR1 CS0 to CS3 A0 to A23 AD0 to AD15 ICNote 3 FLMD0Note 4 FLMD1Note 4 Port CG RG A D converter D A converter PCS0 to PCS7 PCM0 to PCM5 PCT0 to PCT7 PDH0 to PDH7 PDL0 to PDL15 PCD1 to PCD3 P90 to P915 P80 P81 P70 to P715 P40 to P46 P30 to P32 P20 to P22 P00 to P05 ANO0 ANO1 AV REF1 AV DD AV REF0 AV SS ANI0 to ANI15 CLKOUT X...

Page 33: ...re and external sources Eight levels of priority can be specified for these interrupt requests Multiple interrupts can also be processed 6 Clock generator CG Two oscillators one for the main clock fX and the other for the subclock fXT are provided Seven types of clocks fX fX 2 fX 4 fX 8 fX 16 fX 32 and fXT can be generated of which one is supplied to the CPU as the operation clock fCPU The subcloc...

Page 34: ...nd SCK4 pins V850ES SA3 only I 2 C transfers data using the SDA and SCL pins I 2 C is provided only in the µPD703201Y 703204Y 70F3201Y and 70F3204Y UART includes a dedicated baud rate generator 11 A D converter The V850ES SA2 and V850ES SA3 have a high speed high resolution 10 bit A D converter with 12 and 16 analog input pins respectively The A D converter in both products is a successive approxi...

Page 35: ...r P7 12 bit input V850ES SA2 16 bit input V850ES SA3 A D converter analog input P8 2 bit input D A converter analog output P9 16 bit I O External address bus serial interface timer output external interrupt PCDNote 3 bit I O PCM 4 bit I O V850ES SA2 6 bit I O V850ES SA3 External bus interface PCS 4 bit I O V850ES SA2 8 bit I O V850ES SA3 Chip select output PCT 6 bit I O V850ES SA2 8 bit I O V850ES...

Page 36: ...8 EVDD Port 0 port 2 port 3 port 4 port 9 port CD port CM port CS port CT port DH port DL RESET The differences in the pins of the V850ES SA2 and V850ES SA3 are shown below Table 2 2 Differences in Pins of V850ES SA2 and V850ES SA3 V850ES SA2 V850ES SA3 Pin µ3 µ3 µ3 µ3 µ3 µ3 µ3 µ3 P20 SI4 P21 SO4 P22 SCK4 None Provided P712 ANI12 to P715 ANI15 None Provided PCD1 to PCD3 None Provided PCM4 PCM5 Non...

Page 37: ...3 3 bit I O port Can be set to input or output in 1 bit units Can be specified as an N ch open drain port in 1 bit units P31 and P32 only SCK1 P40 SI0 P41 SO0 SDA 490 P42 SCK0 SCL 490 P43 INTP00 TI0 TCLR0 P44 INTP01 TO0 P45 INTP10 TI1 TCLR1 P46 I O Provided Port 4 7 bit I O port Can be set to input or output in 1 bit units Can be specified as an N ch open drain port in 1 bit units P41 and P42 only...

Page 38: ...t in 1 bit units P911 P912 P914 and P915 only A15 SCK3 PCD1 PCD2 PCD3 I O None Port CD 3 bit I O port Can be set to input or output in 1 bit units PCM0 WAIT PCM1 CLKOUT PCM2 HLDAK PCM3 HLDRQ PCM4 PCM5 I O None Port CM 4 bit I O port V850ES SA2 6 bit I O port V850ES SA3 Can be set to input or output in 1 bit units PCS0 CS0 PCS1 CS1 PCS2 CS2 PCS3 CS3 PCS4 PCS5 PCS6 PCS7 I O None Port 10 4 bit I O po...

Page 39: ...I O port V850ES SA2 8 bit I O port V850ES SA3 Can be set to input or output in 1 bit units A23 PDL0 AD0 PDL1 AD1 PDL2 AD2 PDL3 AD3 PDL4 AD4 PDL5 AD5 FLMD1 490 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDL9 AD9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14 AD14 PDL15 I O None Port DL 16 bit I O port Can be set to input or output in 1 bit units AD15 Note µPD70F3201 70F3201Y 70F3204 and 70F3204Y only Remark Pin...

Page 40: ...A22 A23 Output None Address bus for external memory PDH0 to PDH5 PDH6 PDH7 AD0 to AD4 PDL0 to PDL4 AD5 PDL5 FLMD1 490 AD6 to AD15 I O None Address data bus for external memory PDL6 to PDL15 ANI0 P70 ANI1 P71 ANI2 P72 ANI3 P73 ANI4 P74 ANI5 P75 ANI6 P76 ANI7 P77 ANI8 P78 ANI9 P79 ANI10 P710 ANI11 P711 ANI12 P712 ANI13 P713 ANI14 P714 ANI15 Input None Analog voltage input for A D converter P715 ANO0...

Page 41: ...External interrupt request input maskable analog noise elimination P93 A3 INTP00 P43 TI0 TCLR0 INTP01 Capture trigger input TM0 P44 TO0 INTP10 P45 TI1 TCLR1 INTP11 Input Provided Capture trigger input TM1 P46 TO1 NMI Input Provided External interrupt input non maskable analog noise elimination P00 RD Output None Read strobe signal output for external memory PCT4 RESET Input System reset input RXD0...

Page 42: ...0 P44 INTP01 TO1 Timer output TM1 P46 INTP11 TO2 Timer output TM2 P94 A4 TO3 Timer output TM3 P95 A5 TO4 Timer output TM4 P96 A6 TO5 Output Provided Timer output TM5 P97 A7 TXD0 Serial transmit data output UART0 P31 SO1 TXD1 Output Provided Serial transmit data output UART1 P99 A9 VDD Positive power supply pin for internal circuits except subclock oscillator RTC and internal RAM VDDBU Positive pow...

Page 43: ... to A23 A0 to A8 Hi Z Retained Hi Z WAIT CLKOUT L Operates Operates CS0 to CS3 Retained WR0 WR1 RD ASTB Hi Z HLDAK H H L HLDRQ Hi Z 490 Operates Operates Notes 1 Because the bus control pins function alternately as port pins they are initialized to the input mode port mode 2 Indicates the pin status in the idle state that is inserted after the T3 state Remark Hi Z High impedance Retained Status in...

Page 44: ...interrupt request from peripherals Input These pins input an external interrupt request iii TI2 to TI5 timer input 2 to 5 Input These pins input an external count clock to timers 2 to 5 2 P20 to P22 Port 2 V850ES SA3 only 3 state I O Port 2 is a 3 bit I O port that can be set to the input or output mode in 1 bit units Besides functioning as I O port pins P20 to P22 also operate as the I O pins of ...

Page 45: ... receive data 0 Input This pin inputs the serial receive data of UART0 v TXD0 transmit data 0 Output This pin outputs the serial transmit data of UART0 4 P40 to P46 Port 4 3 state I O Port 4 is a 7 bit I O port that can be set to the input or output mode in 1 bit units Besides functioning as I O port pins P40 to P46 also operate as the I O pins of the timer counters and serial interface and as the...

Page 46: ...2 bit input port with all its bits fixed to the input mode Besides functioning as input port pins P70 to P711 also operate as the analog input pins of the A D converter in the control mode However the mode of these pins cannot be changed between the input port mode and analog input mode a Port mode P70 to P711 function as input port pins b Control mode P70 to P711 function as the ANI0 to ANI11 pin...

Page 47: ... the A D converter To prevent these pins malfunctioning due to noise connect a capacitor between these pins and AV66 Make sure that a voltage outside the range of AV66 to AV5 is not applied to any pin that is being used as an input pin of the A D converter If there is a possibility that a noise greater than AV5 or lower than AV66 will be superimposed on any of these pins clamp the pins using a dio...

Page 48: ...s output the serial transmit data of CSI2 and CSI3 iii SCK2 SCK3 serial clock 2 3 3 state I O These pins are the serial clock I O pins of CSI2 and CSI3 iv RXD1 receive data 1 Input This pin inputs the serial receive data of UART1 v TXD1 transmit data 1 Output This pin outputs the serial transmit data of UART1 vi TO2 to TO5 timer output 2 to 5 Output These pins output a pulse signal from timers 2 t...

Page 49: ...us go into a high impedance state in response to a bus hold request While this signal is active the address bus data bus and control bus are in the high impedance state ii HLDRQ hold request Input This pin is used by an external device to request the V850ES SA2 to release the address bus data bus and control bus A signal can be input to this pin asynchronously to CLKOUT When this pin is active the...

Page 50: ... to a bus hold request While this signal is active the address bus data bus and control bus are in the high impedance state ii HLDRQ hold request Input This pin is used by an external device to request the V850ES SA3 to release the address bus data bus and control bus A signal can be input to this pin asynchronously to CLKOUT When this pin is active the V850ES SA3 makes the address bus data bus an...

Page 51: ...ssigned to memory block n n 0 to 3 Each of these signals is active while the bus cycle accessing the corresponding memory block is being executed and inactive in the idle state TI V850ES SA3 Port CS is an 8 bit I O port that can be set to the input or output mode in 1 bit units Besides functioning as I O port pins in the control mode PCS0 to PSC3 also operate as the control signal output pins when...

Page 52: ...t data bus iii RD read strobe Output This is the read strobe signal output pin for the external 16 bit data bus iv ASTB address strobe Output This is the latch strobe signal output pin of the external address bus The output signal goes low at the falling edge of the T1 state in the bus cycle and goes high at the falling edge of the T3 state It is high when the bus cycle is not active V850ES SA3 Po...

Page 53: ... or output mode in 1 bit units by using port mode register DH PMDH b Control mode i A16 to A21 address bus 16 to 21 Output These pins form a 6 bit address output bus to access an external device The output signal changes at the rising edge of the T1 state in the bus cycle The address of the immediately preceding bus cycle is retained when the bus cycle is inactive V850ES SA3 Port DH is an 8 bit po...

Page 54: ...e In the multiplexed bus mode it outputs an address or inputs outputs data In the separate bus mode the bus inputs or outputs data 14 RESET Reset Input The RESET signal is input asynchronously If a signal having a specific low level width is input to this pin regardless of the operation clock the system is reset as a priority over all other operations This pin is used to release the standby mode H...

Page 55: ...upplies positive power Connect all the V pins to the positive power supply 26 V Ground This is the ground pin Connect all the V pins to ground 27 FLMD0 1 Flash programming mode These pins supply positive power for flash memory programming mode These pins are provided only in the µPD70F3201 70F3201Y 70F3204 and 70F3204Y In the normal operation mode connect these pins to V66 28 IC Internally connect...

Page 56: ...INTP11 TO1 5 W Input Independently connect to EVDD or EVSS via a resistor Output Leave open P70 to P711 P712 to P715 ANI0 to ANI11 ANI12 to ANI15 9 P80 P81 ANO0 ANO1 34 Independently connect to AVDD or AVSS via a resistor P90 P91 A0 A1 5 A P92 P93 A2 INTP5 A3 INTP6 5 W P94 to P97 A4 TO2 to A7 TO5 5 A P98 A8 RXD1 5 W P99 A9 TXD1 5 A P910 A10 SI2 5 W P911 A11 SO2 10 E P912 A12 SCK2 10 F P913 A13 SI3...

Page 57: ...4 AD0 to AD4 PDL5 AD5 FLMD1 490 PDL6 to PDL15 AD6 to AD15 5 Input Independently connect to EVDD or EVSS via a resistor Output Leave open AVDD AVREF0 Connect to AVSS via a resistor AVREF1 Connect to AVSS via a resistor AVSS EVDD EVSS FLMD0 490 IC 490 RESET 2 VDD VDDBU VSS VSSBU X1 X2 XT1 16 Connect to VSSBU via a resistor XT2 16 Leave open Notes 1 µPD70F3201 70F3201Y 70F3204 and 70F3204Y only 2 µPD...

Page 58: ...Output disable P ch IN OUT EVDD N ch Input enable Data Output disable P ch IN OUT EVDD N ch Input enable P ch EVDD Pull up enable Type 5 A Data Output disable P ch IN OUT EVDD N ch Input enable Input enable P ch EVDD Pull up enable Type 9 IN Comparator AVREF0 Threshold voltage P ch N ch Input enable Type 10 E Data Output disable P ch IN OUT EVDD N ch P ch EVDD Pull up enable Open drain ...

Page 59: ...l U15905EJ1V0UD 59 Figure 2 1 Pin I O Circuits 2 2 Type 10 F Type 16 P ch Feedback cut off XT1 XT2 Data Output disable Open drain P ch IN OUT EVDD N ch P ch EVDD Pull up enable Input enable Type 34 IN OUT P ch N ch Input enable Analog output voltage ...

Page 60: ...2 2 V to 2 7 V 30 5 ns with subclock fXT 32 768 kHz operation Memory space Program space 64 MB linear Data space 4 GB linear Memory block division function 2 2 4 8 MB total 4 blocks General purpose registers 32 bits 32 registers Internal 32 bit architecture 5 stage pipeline control Multiplication division instruction Saturation operation instruction 32 bit shift instruction 1 clock Load store inst...

Page 61: ... r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero register Assembler reserved register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program counter PSW Program status word ECR Interrupt source register FEPC FEPSW NMI status saving register NMI status saving register EIPC EIPSW Interrupt status saving register Interrupt status saving regis...

Page 62: ...ister for variables Table 3 1 Program Registers Name Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Used as working register to create 32 bit immediate data r2 Register for address data variable if real time OS does not use r2 r3 Stack pointer Used to create a stack frame when a function is called r4 Global pointer Used to access a global variable in the data area r...

Page 63: ... if these registers are accessed 16 CALLT execution status saving register CTPC 17 CALLT execution status saving register CTPSW 18 Exception debug trap status saving register DBPC Note 2 19 Exception debug trap status saving register DBPSW Note 2 20 CALLT base pointer CTBP 21 to 31 Reserved for future function expansion operation is not guaranteed if these registers are accessed Notes 1 Because on...

Page 64: ...ruction next to the one of the instruction under execution except some instructions is saved to EIPC when a software exception or a maskable interrupt occurs The current contents of the PSW are saved to EIPSW Because only one set of interrupt status saving registers is available the contents of these registers must be saved by program when multiple interrupts are enabled Bits 31 to 26 of EIPC and ...

Page 65: ...upts are enabled Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion these bits are always fixed to 0 31 0 FEPC Contents of PC 0 0 Default value 0xxxxxxxH x Undefined 2625 0 0 0 0 31 0 FEPSW Contents of PSW 0 0 Default value 00000xxxH x Undefined 11 12 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 Interrupt source register ECR The interrupt source regi...

Page 66: ...rocessed This bit is set to 1 when an exception occurs Even if this bit is set interrupt requests are acknowledged 0 Exception is not being processed 1 Exception is being processed 5 ID Indicates whether a maskable interrupt can be acknowledged 0 Interrupt enabled 1 Interrupt disabled 4 SATNote Indicates that the result of a saturation operation has overflowed and is saturated Because this is a cu...

Page 67: ...eded Holds value before operation 0 1 Operation result itself 5 CALLT execution status saving registers CTPC and CTPSW CTPC and CTPSW are CALLT execution status saving registers When the CALLT instruction is executed the contents of the program counter PC are saved to CTPC and those of the program status word PSW are saved to CTPSW The contents saved to CTPC are the address of the instruction next...

Page 68: ...debug trap occurs The current contents of the PSW are saved to DBPSW Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion fixed to 0 31 0 DBPC Contents of PC 0 0 Default value 0xxxxxxxH x Undefined 2625 0 0 0 0 31 0 DBPSW Contents of PSW 0 0 Default value 00000xxxH x Undefined 11 12 10 9 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 CALLT base pointer CTBP T...

Page 69: ... after system reset has been released Execution branches to the reset entry address of the internal ROM and then instruction processing is started By setting the PMCDH PMCDL PMCCM PMCCS and PMCCT registers to the control mode using instructions an external device can be connected to the external memory area 2 Flash memory programming mode µ µ µ µPD70F3201 70F3201Y 70F3204 and 70F3204Y In this mode...

Page 70: ...ressing data access It also supports up to 64 MB of linear address space program space for instruction addressing Note however that both the program and data spaces have areas that are prohibited from being used For details refer to Figure 3 2 Figure 3 1 shows the CPU address space Figure 3 1 CPU Address Space Data area 4 GB linear Program area 64 MB linear CPU address space F F F F F F F F H 0 4 ...

Page 71: ...it seems that there are sixty four 64 MB physical address spaces This means that the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 Figure 3 2 Image on Address Space Program space Internal RAM area Use prohibited area Use prohibited area External memory area Internal ROM area external memory area Data space Image 63 Image 1 Image 0 Peripheral I O area Inter...

Page 72: ...wrap around Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is a peripheral I O area instructions cannot be fetched from this area Therefore do not execute an operation in which the result of a branch address calculation affects this area Program space Program space direction direction 0 3 F F F F F E H 0 3 F F F F F F H 0 0 0 0 0 0 0 0 H 0 0 0 0 0 0 0 1 H 2 Data space The result...

Page 73: ...F F H 3 F E C 0 0 0 H 1 0 0 0 0 0 0 H 0 F F F F F F H 0 8 0 0 0 0 0 H 0 7 F F F F F H 0 4 0 0 0 0 0 H 0 3 F F F F F H 0 2 0 0 0 0 0 H 0 1 F F F F F H 0 0 0 0 0 0 0 H 3 F E B F F F H 3 F F F F F F H 3 F F F 0 0 0 H 3 F F E F F F H 3 F F B 0 0 0 H 3 F F A F F F H 3 F E C 0 0 0 H 0 1 F F F F F H 0 1 0 0 0 0 0 H 0 0 F F F F F H 0 0 0 0 0 0 0 H Notes 1 This is the 4 MB space of 0800000H to 0BFFFFFH in ...

Page 74: ...F F F F F H 0 3 F F F 0 0 0 H 0 3 F F E F F F H 3 F F B 0 0 0 H 3 F E A F F F H 0 1 0 0 0 0 0 0 H 0 0 F F F F F F H 0 0 8 0 0 0 0 0 H 0 0 7 F F F F F H 0 0 4 0 0 0 0 0 H 0 0 3 F F F F F H 0 0 2 0 0 0 0 0 H 0 0 1 F F F F F H 0 0 1 0 0 0 0 0 H 0 0 0 F F F F F H 0 0 0 0 0 0 0 0 H Note This is the 4 MB space of 0800000H to 0BFFFFFH in the V850ES SA2 the area of 0C00000H to 0FFFFFFH is the image of 080...

Page 75: ...FFFFFH is reserved as the internal ROM area 1 µ µ µ µPD703201 703201Y 703204 and 703204Y 256 KB are mapped to the following addresses as the physical internal ROM mask ROM 000000H to 03FFFFH 2 µ µ µ µPD70F3201 70F3201Y 70F3204 and 70F3204Y 256 KB are mapped to the following addresses as the physical internal ROM flash memory 000000H to 03FFFFH ...

Page 76: ... Interrupt Exception Table Interrupt Exception Source 00000000H RESET 00000190H INTTM4 00000010H NMI 000001A0H INTTM5 00000040H TRAP0n n 0 to F 000001B0H INTCSI0 00000050H TRAP1n n 0 to F 000001C0H INTIICNote 1 00000060H ILGOP DBG0 000001D0H INTCSI1 00000080H INTWDTM 000001E0H INTSRE0 00000090H INTP0 000001F0H INTSR0 000000A0H INTP1 00000200H INTST0 000000B0H INTP2 00000210H INTCSI2 000000C0H INTP...

Page 77: ...s 3FF0000H to 3FFEFFFH are reserved as the internal RAM area The V850ES SA2 and V850ES SA3 map 16 KB of addresses 3FFB000H to 3FFEFFFH as physical internal RAM Figure 3 5 Internal RAM Area 16 KB Internal RAM area 16 KB Access prohibited area 3 F F B 0 0 0 H 3 F F E F F F H 3 F F 0 0 0 0 H 3 F F A F F F H ...

Page 78: ...be fetched from this area Cautions 1 When a register is accessed in word units a word area is accessed twice in halfword units in the order of lower area and higher area with the lower 2 bits of the address ignored 2 If a register that can be accessed in byte units is accessed in halfword units the higher 8 bits are undefined when the register is read and data is written to the lower 8 bits 3 Addr...

Page 79: ...esses starting from 00000000H unconditionally corresponds to the memory map To use the internal RAM area as the program space access addresses 3FFC000H to 3FFEFFFH 2 Data space With the V850ES SA2 and V850ES SA3 it seems that there are sixty four 64 MB address spaces on the 4 GB CPU address space Therefore the least significant bit bit 25 of a 26 bit address is sign extended to 32 bits and allocat...

Page 80: ...F H 0 4 0 0 0 0 0 0 H 0 3 F F F F F F H 0 3 F F F 0 0 0 H 0 3 F F E F F F H 0 3 F F B 0 0 0 H 0 3 F F A F F F H 0 3 F E C 0 0 0 H 0 3 F E B F F F H 0 1 0 0 0 0 0 0 H 0 0 F F F F F F H 0 0 0 2 0 0 0 0 H 0 0 0 1 F F F F H 0 0 0 0 0 0 0 0 H x F F F F F F F H x F F F F 0 0 0 H x F F F E F F F H x F F F B 0 0 0 H x F F F A F F F H x F F E C 0 0 0 H x F F E B F F F H x 0 1 0 0 0 0 0 H x 0 0 F F F F F H ...

Page 81: ...DH PMCDH FFFFF048H Port mode control register CS PMCCS FFFFF04AH Port mode control register CT PMCCT FFFFF04CH Port mode control register CM PMCCM 00H FFFFF066H Bus size configuration register BSC 5555H FFFFF06EH System wait control register VSWC 77H FFFFF080H DMA source address register 0L DSA0L FFFFF082H DMA source address register 0H DSA0H FFFFF084H DMA destination address register 0L DDA0L FFF...

Page 82: ... 1L IMR1L FFFFF103H Interrupt mask register 1H IMR1H FFH FFFFF104H Interrupt mask register 2 IMR2 FFFFH FFFFF104H Interrupt mask register 2L IMR2L FFFFF105H Interrupt mask register 2H IMR2H FFH FFFFF110H Interrupt control register WDTIC FFFFF112H Interrupt control register PIC0 FFFFF114H Interrupt control register PIC1 FFFFF116H Interrupt control register PIC2 FFFFF118H Interrupt control register ...

Page 83: ...ntrol register ROVIC FFFFF15AH Interrupt control register BRGIC R W 47H FFFFF1FAH In service priority register ISPR R 00H FFFFF1FCH Command register PRCMD W Undefined FFFFF1FEH Power save control register PSC FFFFF200H A D converter mode register ADM FFFFF201H Analog input channel specification register ADS FFFFF202H Power fail comparison mode register PFM FFFFF203H Power fail comparison threshold...

Page 84: ...ort function control register 9 PFC9 0000H FFFFF472H Port function control register 9L PFC9L FFFFF473H Port function control register 9H PFC9H 00H FFFFF484H Data wait control register 0 DWC0 7777H FFFFF488H Address wait control register AWC FFFFH FFFFF48AH Bus cycle control register BCC R W AAAAH FFFFF600H Timer 0 TM0 R FFFFF602H Capture compare register 00 CC00 FFFFF604H Capture compare register ...

Page 85: ...er 5 TMC5 00H FFFFF6C0H Oscillation stabilization time selection register OSTS 04H FFFFF6C1H Watchdog timer time selection register WDCS FFFFF6C2H Watchdog timer mode register WDTM 00H FFFFF6E0H RTC operation control register RTCC 808XH FFFFF6E0H RTC operation control register 0 RTCC0 80H FFFFF6E1H RTC operation control register 1 RTCC1 R W 8XH FFFFF6E2H Sub count register SUBC XXXXH FFFFF6E2H Sub...

Page 86: ...H Correction address register 2 CORAD2 00000000H FFFFF848H Correction address register 2L CORAD2L FFFFF84AH Correction address register 2H CORAD2H 0000H FFFFF84CH Correction address register 3 CORAD3 00000000H FFFFF84CH Correction address register 3L CORAD3L FFFFF84EH Correction address register 3H CORAD3H 0000H FFFFF880H Correction control register CORCN FFFFF8B0H Prescaler mode register PRSM FFF...

Page 87: ...er 0 CSIM0 FFFFFD01H Clocked serial interface clock selection register 0 CSIC0 R W FFFFFD02H Serial I O shift register 0 SIO0 FFFFFD03H Reception only serial I O shift register 0 SIOE0 R FFFFFD04H Clocked serial interface transmit buffer register 0 SOTB0 FFFFFD10H Clocked serial interface mode register 1 CSIM1 FFFFFD11H Clocked serial interface clock selection register 1 CSIC1 R W FFFFFD12H Serial...

Page 88: ...e 1 SOTB4 FFFFFD80H IIC shift registerNote 2 IIC FFFFFD82H IIC control registerNote 2 IICC FFFFFD83H Slave address registerNote 2 SVA FFFFFD84H IIC clock select registerNote 2 IICCL FFFFFD85H IIC function expansion registerNote 2 IICX R W FFFFFD86H IIC status registerNote 2 IICS R FFFFF4BEH External interface mode control register EXIMC R W 00H Notes 1 V850ES SA3 only 2 µPD70F3201 70F3204 70F3201Y...

Page 89: ...Setting data to special registers Set data to the special registers in the following sequence 1 Disable DMA operation 2 Prepare data to be set to the special register in a general purpose register 3 Write the data prepared in 2 to the command register PRCMD 3 Write the setting data to the special register by using the following instructions Store instruction ST SST instruction Bit manipulation ins...

Page 90: ...mand register PRCMD The command register PRCMD is an 8 bit register that protects the registers that may seriously affect the application system from being written so that the system does not inadvertently stop due to a program hang up The first write access to a special register power save control register PSC is valid after data has been written in advance to the PRCMD register In this way the v...

Page 91: ...register is read including execution of a bit manipulation instruction between a write access to the PRCMD register and a write access to a special register other than the WDTM register PCC PSC and BPS registers such as an access to the internal RAM the PRERR flag is not set and data can be written to the special register b Clear condition PRERR 0 i When 0 is written to the PRERR flag of the SYS r...

Page 92: ...g the port related registers 1 System wait control register VSWC The system wait control register VSWC controls wait of bus access to the internal peripheral I O registers Three clocks are required to access an internal peripheral I O register without a wait cycle The V850ES SA2 and V850ES SA3 require wait cycles according to the operating frequency Set the following value to the VSWC register in ...

Page 93: ...ports 14 pins I O ports 68 pins I O pins function alternately as other peripheral functions Can be set to input or output mode in 1 bit units 4 1 2 V850ES SA3 Input ports 18 pins I O ports 84 pins I O pins function alternately as other peripheral functions Can be set to input or output mode in 1 bit units ...

Page 94: ...put port pins of which 14 are input only port pins ports 0 3 4 7 to 9 CM CS CT DH and DL The port configuration is shown below Figure 4 1 Port Configuration V850ES SA2 P00 P05 Port 0 P90 P915 Port 9 PCM0 PCM3 Port CM PCS0 PCS3 Port CS PCT0 PCT1 PCT4 PCT7 Port CT PDH0 PDH5 Port DH PDL0 PDL15 Port DL P30 P32 Port 3 P40 P46 Port 4 P70 P711 Port 7 P80 P81 Port 8 ...

Page 95: ...input only port pins ports 0 2 to 4 7 to 9 CD CM CS CT DH and DL The port configuration is shown below Figure 4 2 Port Configuration V850ES SA3 P00 P05 Port 0 P90 P915 Port 9 PCD1 PCD3 Port CD PCM0 PCM5 Port CM PCS0 PCS7 Port CS PCT0 PCT7 Port CT PDH0 PDH7 Port DH PDL0 PDL15 Port DL P30 P32 Port 3 P20 P22 Port 2 P40 P46 Port 4 P70 P715 Port 7 P80 P81 Port 8 ...

Page 96: ...9 CM CS CT DH DL Pull up resistor option register PUn n 0 3 4 9 Ports I O 68 pins Input 14 pins Pull up resistor Software controlled 32 resistors Table 4 2 Port Configuration V850ES SA3 Item Configuration Control registers Port mode register PMn n 0 3 4 9 CM CS CT DH DL Pull up resistor option register PUn n 0 2 3 4 9 Ports I O 84 pins Input 18 pins Pull up resistor Software controlled 35 resistor...

Page 97: ...de or control mode alternate function in 1 bit units by using port mode control register 0 PMC0 An internal pull up resistor can be connected in 1 bit units by using pull up resistor option register 0 PU0 The valid edge of the external interrupt alternate function can be set in 1 bit units by using external interrupt falling edge specification register 0 INTF0 and external interrupt rising edge sp...

Page 98: ...evel at that time is read When written the data written to P0 is written The input pin is not affected In output mode When port 0 P0 is read the value of P0 is read When a value is written to P0 it is immediately output 2 After reset an undefined value pin input level is read from P0 in the input mode When P0 is read in the output mode 00H value of the output latch is read b Port mode register 0 P...

Page 99: ...pin I O port INTP0 TI2 output PMC01 0 1 Specifies operation mode of P01 pin I O port NMI input PMC00 0 1 Specifies operation mode of P00 pin After reset 00H R W Address FFFFF440H Caution A register for selects external interrupts INTP0 to INTP3 and timer inputs TM2 to TM5 is not provided When using port 0 to input an external interrupt specify the valid edge of the interrupt request by using the I...

Page 100: ...fter reset 00H R W Address FFFFFC40H e External interrupt falling edge specification register 0 INTF0 This 8 bit register specifies detection of the falling edge of the external interrupt pins It can be read or written in 8 bit or 1 bit units Caution Set the port mode after clearing the INTF0n and INTR0n bits to 0 when switching from the external interrupt function alternate function to the port f...

Page 101: ...he INTF0n and INTR0n bits to 0 when switching from the external interrupt function alternate function to the port function because an edge may be detected 0 INTR0 0 INTR05 INTR04 INTR03 INTR02 INTR01 INTR00 After reset 00H R W Address FFFFFC20H Remark For how to specify a valid edge refer to Table 4 4 Table 4 4 Specifying Valid Edge INTF0n INTR0n Specifies valid edge n 0 to 5 0 0 Detects no edge 0...

Page 102: ...n WRINTF INTF0n Selector Selector WRPU PU0n WRPM PM0n P0n Noise elimination edge detection WRINTR INTR0n PMC0 INTF0 PU0 PM0 P0 INTR0 EVDD P ch Remarks 1 P0 Port register 0 PM0 Port mode register 0 PMC0 Port mode control register 0 PU0 Pull up resistor option register 0 INTR0 External interrupt rising edge specification register 0 INTF0 External interrupt falling edge specification register 0 2 n 0...

Page 103: ...MC0n WRINTF INTF0n Selector Selector WRPU PU0n WRPM PM0n P0n Noise elimination edge detection Noise elimination edge detection WRINTR INTR0n PMC0 INTF0 PU0 PM0 P0 INTR0 EVDD P ch Remarks 1 P0 Port register 0 PM0 Port mode register 0 PMC0 Port mode control register 0 PU0 Pull up resistor option register 0 INTR0 External interrupt rising edge specification register 0 INTF0 External interrupt falling...

Page 104: ... 1 bit units by using port mode register 2 PM2 Can be set to the port mode or control mode alternate function in 1 bit units by using port mode control register 2 PMC2 N ch open drain output can be set in 1 bit units by using port function register 2 PF2 An internal pull up resistor can be connected in 1 bit units by using pull up resistor option register 2 PU2 Port 2 has an alternate function as ...

Page 105: ... level at that time is read When written the data written to P2 is written The input pin is not affected In output mode When port 2 P2 is read the value of P2 is read When a value is written to P2 it is immediately output 2 After reset an undefined value pin input level is read from P2 in the input mode When P2 is read in the output mode 00H value of the output latch is read b Port mode register 2...

Page 106: ...port SI4 input PMC20 0 1 Specifies operation mode of P20 pin After reset 00H R W Address FFFFF444H d Port function register 2 PF2 This 8 bit register specifies normal output or N ch open drain output It can be read or written in 8 bit or 1 bit units 0 Normal output N ch open drain output PF2n 0 1 Controls normal output or N ch open drain output n 1 2 PF2 0 0 0 0 PF22 PF21 0 After reset 00H R W Add...

Page 107: ... PU2 This is an 8 bit register that specifies connection of an internal pull up resistor This register can be read or written in 8 bit or 1 bit units 0 Not connected Connected PU2n 0 1 Controls connection of internal pull up resistor n 0 to 2 PU2 0 0 0 0 PU22 PU21 PU20 After reset 00H R W Address FFFFFC44H ...

Page 108: ... Figure 4 5 Block Diagram of P20 Internal bus WRPMC RD Address SI4 input WRPORT P20 SI4 PMC20 P20 Selector Selector WRPU PU20 WRPM PM20 PMC2 P2 PU2 PM2 EVDD P ch Remark P2 Port register 2 PM2 Port mode register 2 PMC2 Port mode control register 2 PU2 Pull up resistor option register 2 ...

Page 109: ...21 Internal bus WRPMC RD Address SO4 output WRPORT P21 SO4 PMC21 Selector Selector Selector WRPU PU21 WRPM PM21 P21 WRPF PF21 PMC2 PU2 PM2 P2 PF2 EVDD P ch EVDD EVSS P ch N ch Remark P2 Port register 2 PM2 Port mode register 2 PMC2 Port mode control register 2 PU2 Pull up resistor option register 2 ...

Page 110: ...CK4 output SCK4 input SCK4 output enable signal WRPORT P22 SCK4 PMC22 Selector Selector Selector WRPU PU22 WRPM PM22 P22 WRPF PF22 PMC2 PU2 PM2 P2 PF2 EVDD P ch EVDD EVSS P ch N ch Remark P2 Port register 2 PM2 Port mode register 2 PMC2 Port mode control register 2 PF2 Port function register 2 PU2 Pull up resistor option register 2 ...

Page 111: ...t to the port mode or control mode alternate function in 1 bit units by using port mode control register 3 PMC3 Control mode 1 or control mode 2 can be specified in 1 bit units by using port function control register 3 PFC3 N ch open drain output can be set in 1 bit units by using port function register 3 PF3 An internal pull up resistor can be connected in 1 bit units by using pull up resistor op...

Page 112: ... level at that time is read When written the data written to P3 is written The input pin is not affected In output mode When port 3 P3 is read the value of P3 is read When a value is written to P3 it is immediately output 2 After reset an undefined value pin input level is read from P3 in the input mode When P3 is read in the output mode 00H value of the output latch is read b Port mode register 3...

Page 113: ...D0 output PMC31 0 1 Specifies operation mode of P31 pin I O port SI1 RXD0 input PMC30 0 1 Specifies operation mode of P30 pin After reset 00H R W Address FFFFF446H d Port function control register 3 PFC3 This 8 bit register specifies control mode 1 or control mode 2 It can be read or written in 8 bit or 1 bit units PFC3 After reset 00H R W Address FFFFF466H 0 0 0 0 0 0 PFC31 PFC30 SO1 output TXD0 ...

Page 114: ...00H R W Address FFFFFC66H Cautions 1 The N ch open drain output voltage is the normal voltage not the medium voltage 2 PF3n 1 is enabled only in the following cases Otherwise the setting is prohibited n 1 SO1 n 2 SCK1 f Pull up resistor option register 3 PU3 This is an 8 bit register that specifies connection of an internal pull up resistor This register can be read or written in 8 bit or 1 bit un...

Page 115: ...l bus WRPMC RD Address SI1 input RXD0 input WRPORT P30 SI1 RXD0 PMC30 P30 Selector Selector Selector WRPU PU30 WRPM PM30 WRPFC PFC30 PMC3 P3 PU3 PM3 PFC3 EVDD P ch Remark P3 Port register 3 PM3 Port mode register 3 PMC3 Port mode control register 3 PFC3 Port function control register 3 PU3 Pull up resistor option register 3 ...

Page 116: ... WRPORT P31 SO1 TXD0 PMC31 WRPMC PFC31 Selector Selector Selector Selector WRPU PU31 WRPM PM31 P31 WRPF PF31 PMC3 PFC3 PU3 PM3 P3 PF3 EVDD P ch EVDD EVSS P ch N ch Remark P3 Port register 3 PM3 Port mode register 3 PMC3 Port mode control register 3 PFC3 Port function control register 3 PF3 Port function register 3 PU3 Pull up resistor option register 3 ...

Page 117: ...output SCK1 input SCK1 output enable signal WRPORT P32 SCK1 PMC32 Selector Selector Selector WRPU PU32 WRPM PM32 P32 WRPF PF32 PMC3 PU3 PM3 P3 PF3 EVDD P ch EVDD EVSS P ch N ch Remark P3 Port register 3 PM3 Port mode register 3 PMC3 Port mode control register 3 PFC3 Port function control register 3 PU3 Pull up resistor option register 3 ...

Page 118: ... in 1 bit units by using port mode control register 4 PMC4 Control mode 1 or control mode 2 can be specified in 1 bit units by using port function control register 4 PFC4 N ch open drain output can be set to 1 bit units by using port function register 4 PF4 The internal pull up resistor can be connected in 1 bit units by using pull up resistor option register 4 PU4 Port 4 has an alternate function...

Page 119: ...evel at that time is read When written the data written to P4 is written The input pin is not affected In output mode When port 4 P4 is read the value of P4 is read When a value is written to P4 it is immediately output 2 After reset an undefined value pin input level is read from P4 in the input mode When P4 is read in the output mode 00H value of the output latch is read b Port mode register 4 P...

Page 120: ...0 TI0 TCLR0 inputNote PMC43 0 1 Specifies operation mode of P43 pin After reset 00H R W Address FFFFF448H I O port SCK0 I O PMC42 0 1 Specifies operation mode of P42 pin I O port SO0 output PMC41 0 1 Specifies operation mode of P41 pin I O port SI0 input PMC40 0 1 Specifies operation mode of P40 pin Cautions 1 To use INTP0n perform the following setting CMSn0 bit of TMCn1 register 0 ETIn bit of TM...

Page 121: ...e of P46 pin in control mode INTP01 input TO0 inputNote 1 PFC44 0 1 Specifies operation mode of P44 pin in control mode SCK0 I O SCL I ONote 2 PFC42 0 1 Specifies operation mode of P42 pin in control mode SO0 output SDA I ONote 2 PFC41 0 1 Specifies operation mode of P41 pin in control mode Notes 1 Setting of PCF44 and PCF46 1 is enabled only when TOn output is enabled ENTOn of TMCn1 register 1 n ...

Page 122: ...e N ch open drain output voltage is the normal voltage not the medium voltage 2 PF4n 1 is enabled only in the following cases Otherwise the setting is prohibited n 1 SO0 SDA n 2 SCK0 SCL 3 Be sure to set N ch open drain output when using I 2 C f Pull up resistor option register 4 PU4 This is an 8 bit register that specifies connection of an internal pull up resistor This register can be read or wr...

Page 123: ...11 Block Diagram of P40 Internal bus WRPMC RD Address Input signal in control mode WRPORT P40 SI0 PMC40 P40 Selector Selector WRPU PU40 WRPM PM40 PMC4 P4 PU4 PM4 EVDD P ch Remark P4 Port register 4 PM4 Port mode register 4 PMC4 Port mode control register 4 PU4 Pull up resistor option register 4 ...

Page 124: ... input WRPORT P41 SO0 SDA PMC41 WRPMC PFC41 Selector Selector Selector Selector WRPU PU41 WRPM PM41 P41 WRPF PF41 PMC4 PFC4 PU4 PM4 P4 PF4 EVDD P ch EVDD EVSS P ch N ch Remark P4 Port register 4 PM4 Port mode register 4 PMC4 Port mode control register 4 PFC4 Port function control register 4 PF4 Port function register 4 PU4 Pull up resistor option register 4 ...

Page 125: ...enable signal WRPORT P42 SCK0 SCL PMC42 WRPMC PFC42 Selector Selector Selector Selector WRPU PU42 WRPM PM42 P42 WRPF PF42 PMC4 PFC4 PU4 PM4 P4 PF4 EVDD P ch EVDD EVSS P ch N ch SCL output Remark P4 Port register 4 PM4 Port mode register 4 PMC4 Port mode control register 4 PFC4 Port function control register 4 PF4 Port function register 4 PU4 Pull up resistor option register 4 ...

Page 126: ... RD Address INTP00 TI0 TCLR0 INTP10 TI1 TCLR1 input WRPORT P43 INTP00 TI0 TCLR0 P45 INTP10 TI1 TCLR1 PMC4n P4n Selector Selector WRPU PU4n WRPM PM4n PMC4 P4 PU4 PM4 EVDD P ch Noise elimination Remarks 1 P4 Port register 4 PM4 Port mode register 4 PMC4 Port mode control register 4 PU4 Pull up resistor option register 4 2 n 3 or 5 ...

Page 127: ...put WRPORT P44 INTP01 TO0 P46 INTP11 TO1 PMC4n Selector Selector Selector WRPU PU4n WRPM PM4n P4n WRPF PFC4n PMC4 PU4 PM4 P4 PFC4 EVDD P ch INTP01 INTP11 input Noise elimination Remarks 1 P4 Port register 4 PM4 Port mode register 4 PMC4 Port mode control register 4 PFC4 Port function control register 4 PU4 Pull up resistor option register 4 2 n 4 or 6 ...

Page 128: ...of port 7 Input data can be specified in 1 bit units by using port register 7 P7 Port 7 has an alternate function as the following pins Table 4 8 Alternate Function Pins of Port 7 Pin Name Alternate Function Pin I O PULLNote 1 Remark P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P77 ANI5 P76 ANI6 P77 ANI7 P78 ANI8 P79 ANI9 P710 ANI10 P711 ANI11 P712Note 2 ANI12Note 2 P713Note 2 ANI13Note 2 P714Note...

Page 129: ... V850ES SA2 n 0 to 12 V850ES SA3 n 0 to 15 P7 After reset Undefined R Address FFFFF40EH FFFFF40FH P77 P76 P75 P74 P73 P72 P71 P70 P715Note P714Note P713Note P712Note P711 P710 P79 P78 8 9 10 11 12 13 14 15 Note Bits 15 to 12 are valid only in the V850ES SA3 These bits are undefined in the V850ES SA2 Caution Do not read the P7 register during A D conversion Remarks 1 If port 7 P7 is read the pin le...

Page 130: ...ollowing pins Table 4 9 Alternate Function Pins of Port 8 Pin Name Alternate Function Pin I O PULLNote Remark P80 ANO0 Port 8 P81 ANO1 Input None Note Software pull up function 2 Register a Port register 8 P8 Port register 8 P8 is an 8 bit register that is used to read the pin level This register is read only in 8 bit or 1 bit units 0 Inputs low level Inputs high level P8n 0 1 Reads input data n 0...

Page 131: ...CHAPTER 4 PORT FUNCTIONS Preliminary User s Manual U15905EJ1V0UD 131 3 Block diagram Figure 4 17 Block Diagram of P80 and P81 Internal bus RD P80 ANO0 P81 ANO1 P ch N ch ANO0 ANO1 output ...

Page 132: ...ort function register 9 PF9 Control mode 1 or control mode 2 can be specified in 1 bit units by using port function control register 9 PFC9 The internal pull up resistor can be connected in 1 bit units by using pull up resistor option register 9 PU9 The valid edge of the external interrupt alternate function can be set in 1 bit units by using external interrupt falling edge specification register ...

Page 133: ...that time is read When written the data written to P9 is written The input pin is not affected In output mode When port 9 P9 is read the value of P9 is read When a value is written to P9 it is immediately output 2 After reset an undefined value pin input level is read from P9 in the input mode When P9 is read in the output mode 00H value of the output latch is read b Port mode register 9 PM9 This ...

Page 134: ...cifies operation mode of P915 pin PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 After reset 0000H R W Address FFFFF452H FFFFF453H PMC915 PMC9 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 8 9 10 11 12 13 14 15 I O port A14 SO3 output PMC914 0 1 Specifies operation mode of P914 pin I O port A11 SO2 output PMC911 0 1 Specifies operation mode of P610 pin I O port A10 SI2 input PMC910 0 1 Specifies...

Page 135: ...1 Specifies operation mode of P96 pin I O port A5 TO3 output PMC95 0 1 Specifies operation mode of P95 pin I O port A4 TO2 output PMC94 0 1 Specifies operation mode of P94 pin I O port A3 INTP6 I O PMC93 0 1 Specifies operation mode of P93 pin I O port A2 INTP5 I O PMC92 0 1 Specifies operation mode of P92 pin I O port A1 output PMC91 0 1 Specifies operation mode of P91 pin I O port A0 output PMC9...

Page 136: ...P915 pin in control mode A14 output with separate bus SO3 output PFC914 0 1 Specifies operation mode of P914 pin in control mode A13 output with separate bus SI3 input PFC913 0 1 Specifies operation mode of P913 pin in control mode A12 output with separate bus SCK2 I O PFC912 0 1 Specifies operation mode of P912 pin in control mode After reset 0000H R W Address FFFFF472H FFFFF473H PFC97 PFC96 PFC9...

Page 137: ...separate bus TO4 output PFC96 0 1 Specifies operation mode of P96 pin in control mode A5 output with separate bus TO3 output PFC95 0 1 Specifies operation mode of P95 pin in control mode A4 output with separate bus TO2 output PFC94 0 1 Specifies operation mode of P94 pin in control mode A3 output with separate bus INTP6 input PFC93 0 1 Specifies operation mode of P93 pin in control mode A2 output ...

Page 138: ...n 11 12 14 or 15 Cautions 1 The N ch open drain output voltage is the normal voltage not the medium voltage 2 PF9n 1 is enabled only in the following cases Otherwise the setting is prohibited n 1 SO2 n 2 SCK2 n 4 SO3 n 5 SCK3 f Pull up resistor option register 9 PU9 This is a 16 bit register that specifies connection of an internal pull up resistor This register can be read or written only in 16 b...

Page 139: ...F9L FFFFFC12H 0 0 0 0 INTF93 INTF92 0 0 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 Remark For how to specify a valid edge refer to Table 4 11 h External interrupt rising edge specification register 9 INTR9 This 16 bit register specifies detection of the rising edge of the external interrupt pins It can be read or written only in 16 bit units If the higher 8 bits of the INTR9 register are used as INTR9H...

Page 140: ...able 4 11 Specifying Valid Edge INTF9n INTR9n Specifies valid edge n 2 or 3 0 0 Detects no edge 0 1 Rising edge 1 0 Falling edge 1 1 Both edges Caution When INTP5 and INTP6 are not used be sure to clear INTF9n and INTR9n to 00 Remark n 2 or 3 Control of INTP5 or INTP6 pin ...

Page 141: ...A0 A1 output Output buffer OFF signal WRPORT P90 A0 P91 A1 PMC9n P9n Selector Selector Selector Selector WRPM PM9n WRPU PU9n PMC9 P9 PM9 PU9 EVDD P ch Remarks 1 P9 Port register 9 PM9 Port mode register 9 PMC9 Port mode control register 9 PU9 Pull up resistor option register 9 Output buffer OFF signal Signal that is active in the IDLE STOP mode 2 n 0 or 1 ...

Page 142: ... WREGN INTF9n WREGP INTR9n PMC9 PFC9 PU9 PM9 P9 INTF9 INTR9 EVDD P ch INTP5 INTP6 input Noise elimination edge detection Remarks 1 P9 Port register 9 PM9 Port mode register 9 PMC9 Port mode control register 9 PFC9 Port function control register 9 PU9 Pull up resistor option register 9 INTR9 External interrupt rising edge specification register 9 INTF9 External interrupt falling edge specification ...

Page 143: ...4 TO2 P95 A5 TO3 P96 A6 TO4 P97 A7 TO5 P99 A9 TXD1 PMC9n P9n Selector Selector Selector Selector Selector WRPU PU9n WRPM PM9n WRPFC PFC9n PMC9 P9 PU9 PM9 PFC9 EVDD P ch Remarks 1 P9 Port register 9 PM9 Port mode register 9 PMC9 Port mode control register 9 PF9 Port function register 9 PU9 Pull up resistor option register 9 Output buffer OFF signal Signal that is active in the IDLE STOP mode or dur...

Page 144: ...WRPORT P98 A8 RXD1 P910 A10 SI2 P913 A13 SI3 PMC9n P9n Selector Selector Selector Selector WRPU PU9n WRPM PM9n WRPFC PFC9n PMC9 P9 PU9 PM9 PFC9 EVDD P ch Remarks 1 P9 Port register 9 PM9 Port mode register 9 PMC9 Port mode control register 9 PF9 Port function register 9 PU9 Pull up resistor option register 9 Output buffer OFF signal Signal that is active in the IDLE STOP mode or during bus hold 2 ...

Page 145: ...tor Selector Output buffer OFF signal Selector Selector WRPFC PU9n WRPM PM9n P9n WRPFC PF9n PMC9 PFC9 PU9 PM9 P9 PF9 EVDD P ch EVDD EVSS P ch N ch Remarks 1 P9 Port register 9 PM9 Port mode register 9 PMC9 Port mode control register 9 PFC9 Port function control register 9 PF9 Port function register 9 PU9 Pull up resistor option register 9 Output buffer OFF signal Signal that is active in the IDLE ...

Page 146: ...tput enable signal of SCK2 and SCK3 Output buffer OFF signal Selector Selector WRPFC PU9n WRPM PM9n P9n WRPFC PF9n PMC9 PFC9 PU9 PM9 P9 PF9 EVDD P ch EVDD EVSS P ch N ch Selector Remarks 1 P9 Port register 9 PM9 Port mode register 9 PMC9 Port mode control register 9 PFC9 Port function control register 9 PF9 Port function register 9 PU9 Pull up resistor option register 9 Output buffer OFF signal Si...

Page 147: ...50ES SA2 V850ES SA3 3 bit I O port 1 Functions of port CD V850ES SA3 Input output data can be specified in 1 bit units by using port register CD PCD Can be set to the input or output mode in 1 bit units by using port mode register CD PMCD Port CD has no alternate function pins Table 4 12 Alternate Function Pins of Port CD V850ES SA3 Pin Name Alternate Function Pin I O PULLNote Remark PCD1 PCD2 Por...

Page 148: ... level at that time is read When written the data written to PCD is written The input pin is not affected In output mode When port CD PCD is read the value of PCD is read When a value is written to PCD it is immediately output 2 After reset an undefined value pin input level is read from PCD in the input mode When PCD is read in the output mode 00H value of the output latch is read b Port mode reg...

Page 149: ...r s Manual U15905EJ1V0UD 149 3 Block diagram Figure 4 24 Block Diagram of PCD1 to PCD3 Internal bus WRPM RD Address WRPORT PCD1 to PCD3 PMCDn PCDn PMCD PCD Selector Selector Remarks 1 PCD Port register CD PMCD Port mode register CD 2 n 1 to 3 ...

Page 150: ...fied in 1 bit units by using port register CM PCM Can be set to the input or output mode in 1 bit units by using port mode register CM PMCM Can be set to the port mode or control mode alternate function in 1 bit units by using port mode control register CM PMCCM Port CM has an alternate function as the following pins Table 4 13 Alternate Function Pins of Port CM Pin Name Alternate Function Pin I O...

Page 151: ...evel at that time is read When written the data written to PCM is written The input pin is not affected In output mode When port CM PCM is read the value of PCM is read When a value is written to PCM it is immediately output 2 After reset an undefined value pin input level is read from PCM in the input mode When PCM is read in the output mode 00H value of the output latch is read b Port mode regis...

Page 152: ...d or written in 8 bit or 1 bit units 0 PMCCM 0 0 0 PMCCM3 PMCCM2 PMCCM1 PMCCM0 I O port HLDQR input PMCCM3 0 1 Specifies operation mode of PCM3 pin I O port HLDAK input PMCCM2 0 1 Specifies operation mode of PCM2 pin I O port CLKOUT output PMCCM1 0 1 Specifies operation mode of PCM1 pin I O port WAIT input PMCCM0 0 1 Specifies operation mode of PCM0 pin After reset 00H R W Address FFFFF04CH ...

Page 153: ...ram Figure 4 25 Block Diagram of PCM0 and PCM3 Internal bus WRPMC RD Address WAIT HLDRQ input WRPORT PCM0 WAIT PCM3 HLDRQ PMCCMn PCMn Selector Selector WRPM PMCMn PMCCM PCM PMCM Remarks 1 PCM Port register CM PMCM Port mode register CM PMCCM Port mode control register CM 2 n 0 or 3 ...

Page 154: ... Block Diagram of PCM1 and PCM2 Internal bus WRPMC RD Address CLKOUT HLDAK output WRPORT PCM1 CLKOUT PCM2 HLDAK PMCCMn PCMn PCM Selector Selector Selector WRPM PMCMn PMCCM PMCM Remarks 1 PCM Port register CM PMCM Port mode register CM PMCCM Port mode control register CM 2 n 1 or 2 ...

Page 155: ...inary User s Manual U15905EJ1V0UD 155 Figure 4 27 Block Diagram of PCM4 and PCM5 Internal bus WRPM RD Address WRPORT PCM4 PCM5 PMCMn PCMn PMCM PCM Selector Selector Remarks 1 PCM Port register CM PMCM Port mode register CM 2 n 4 or 5 ...

Page 156: ... 1 bit units by using port register CS PCS Can be set to the input or output mode in 1 bit units by using port mode register CS PMCS Can be set to the port mode or control mode alternate function in 1 bit units by using port mode control register CS PMCCS Port CS has an alternate function as the following pins Table 4 14 Alternate Function Pins of Port CS Pin Name Alternate Function Pin I O PULLNo...

Page 157: ...vel at that time is read When written the data written to PCS is written The input pin is not affected In output mode When port CS PCS is read the value of PCS is read When a value is written to PCS it is immediately output 2 After reset an undefined value pin input level is read from PCS in the input mode When PCS is read in the output mode 00H value of the output latch is read b Port mode regist...

Page 158: ...gister CS PMCCS This is an 8 bit register that specifies the port mode or control mode It can be read or written in 8 bit or 1 bit units 0 I O port CSn output PMCCSn 0 1 Specifies operation mode of PCSn pin n 0 to 3 PMCCS 0 0 0 PMCCS3 PMCCS2 PMCCS1 PMCCS0 After reset 00H R W Address FFFFF048H ...

Page 159: ...Figure 4 28 Block Diagram of PCS0 to PCS3 Internal bus WRPMC RD Address CS0 to CS3 output WRPORT PCS0 CS0 to PCS3 CS3 PMCCSn PCSn PCS Selector Selector Selector WRPM PMCSn PMCCS PMCS Remarks 1 PCS Port register CS PMCS Port mode register CS PMCCS Port mode control register CS 2 n 0 to 3 ...

Page 160: ...nary User s Manual U15905EJ1V0UD 160 Figure 4 29 Block Diagram of PCS4 to PCS7 Internal bus WRPM RD Address WRPORT PCS4 to PCS7 PMCSn PCSn PMCS PCS Selector Selector Remarks 1 PCS Port register CS PMCS Port mode register CS 2 n 4 to 7 ...

Page 161: ...ut output data can be specified in 1 bit units by using port register CT PCT Can be set to the input or output mode in 1 bit units by using port mode register CT PMCT Can be set to the port mode or control mode alternate function in 1 bit units by using port mode control register CT PMCCT Table 4 15 Alternate Function Pins of Port CT Pin Name Alternate Function Pin I O PULLNote 1 Remark PCT0 WR0 P...

Page 162: ...vel at that time is read When written the data written to PCT is written The input pin is not affected In output mode When port CT PCT is read the value of PCT is read When a value is written to PCT it is immediately output 2 After reset an undefined value pin input level is read from PCT in the input mode When PCT is read in the output mode 00H value of the output latch is read b Port mode regist...

Page 163: ...ead or written in 8 bit or 1 bit units 0 PMCCT PMCCT6 0 PMCCT4 0 0 PMCCT1 PMCCT0 I O port ASTB output PMCCT6 0 1 Specifies operation mode of PCT6 pin I O port RD output PMCCT4 0 1 Specifies operation mode of PCT4 pin I O port WR1 output PMCCT1 0 1 Specifies operation mode of PCT1 pin I O port WR0 output PMCCT0 0 1 Specifies operation mode of PCT0 pin After reset 00H R W Address FFFFF04AH ...

Page 164: ...Diagram of PCT0 PCT1 PCT4 and PCT6 Internal bus WRPMC RD Address WR0 WR1 RD ASTB output WRPORT PCT0 WR0 PCT1 WR1 PCT4 RD PCT6 ASTB PMCCTn PCTn PCT Selector Selector Selector WRPM PMCTn PMCCT PMCT Remarks 1 PCT Port register CT PMCT Port mode register CT PMCCT Port mode control register CT 2 n 0 1 4 or 6 ...

Page 165: ... Manual U15905EJ1V0UD 165 Figure 4 31 Block Diagram of PCT2 PCT3 PCT5 and PCT7 Internal bus WRPM RD Address WRPORT PCT2 PCT3 PCT5 PCT7 PMCTn PCTn PMCT PCT Selector Selector Remarks 1 PCT Port register CT PMCT Port mode register CT 2 n 2 3 5 or 7 ...

Page 166: ...nits by using port register DH PDH Can be set to the input or output mode in 1 bit units by using port mode register DH PMDH Can be set to the port mode or control mode alternate function in 1 bit units by using port mode control register DH PMCDH Port DH has an alternate function as the following pins Table 4 16 Alternate Function Pins of Port DH Pin Name Alternate Function Pin I O PULLNote 1 Rem...

Page 167: ...vel at that time is read When written the data written to PDH is written The input pin is not affected In output mode When port DH PDH is read the value of PDH is read When a value is written to PDH it is immediately output 2 After reset an undefined value pin input level is read from PDH in the input mode When PDH is read in the output mode 00H value of the output latch is read b Port mode regist...

Page 168: ...in 8 bit or 1 bit units I O port Am output address bus output V850ES SA2 m 16 to 21 V850ES SA3 m 16 to 23 PMCDHn 0 1 Specifies operation mode of PDHn pin V850ES SA2 n 0 to 5 V850ES SA3 n 0 to 7 PMCDH7Note PMCDH6Note PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 After reset 00H R W Address FFFFF046H PMCDH Note Bits 7 and 6 are provided in the V850ES SA3 only Be sure to clear these bits to 0 in the V850...

Page 169: ...o PDH7 A23 PMCDHn PDHn Selector Selector Selector Selector WRPM PMDHn WRPU PUDHn PMCDH PDH PMDH PUDH EVDD P ch Output signal in control mode Output buffer OFF signal Remarks 1 PDH Port register DH PMDH Port mode register DH PMCDH Port mode control register DH PUDH Pull up resistor option register DH Output buffer OFF signal Signal that is active in IDLE STOP mode 2 n 0 to 7 ...

Page 170: ...ort mode or control mode alternate function in 1 bit units by using port mode control register DL PMCDL Port DL has an alternate function as the following pins Table 4 17 Alternate Function Pins of Port DL Pin Name Alternate Function Pin I O PULLNote 1 Remark PDL0 AD0 PDL1 AD1 PDL2 AD2 PDL3 AD3 PDL4 AD4 PDL5 AD5 FLMD1Note 2 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDLDL AD9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL1...

Page 171: ...s read the pin level at that time is read When written the data written to PDL is written The input pin is not affected In output mode When port DL PDL is read the value of PDL is read When a value is written to PDL it is immediately output 2 After reset an undefined value pin input level is read from PDL in the input mode When PDL is read in the output mode 0000H value of the output latch is read...

Page 172: ...ever PMCDLH and PMCDLL can be read or written in 8 bit units I O port ADn output address data bus input output PMCDLn 0 1 Specifies operation mode of PDLn pin n 0 to 15 PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 After reset 0000H R W Address FFFFF044H FFFFF045H PMCDL15 PMCDL PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 8 9 10 11 12 13 14 15 Caution Do not specify AD8 to AD15 wh...

Page 173: ... enable signal of AD0 to AD15 Input of AD0 to AD15 Output enable signal of AD0 to AD15 Output buffer OFF signal WRPORT PDL0 AD0 to PDL15 AD15 PMCDLn PDLn Selector Selector Selector Selector WRPM PMDLn PMCDL PDL PMDL Remarks 1 PDL Port register DL PMDL Port mode register DL PMCDL Port mode control register DL Output buffer OFF signal Signal that is active in IDLE STOP mode 2 n 0 to 15 ...

Page 174: ...M32 Setting not needed PM40 Setting not needed PM41 Setting not needed PM41 Setting not needed PM42 Setting not needed PM42 Setting not needed Pnx Bit of Pn Register P00 Setting not needed P01 Setting not needed P01 Setting not needed P02 Setting not needed P02 Setting not needed P03 Setting not needed P03 Setting not needed P04 Setting not needed P04 Setting not needed P05 Setting not needed P05 ...

Page 175: ...tting not needed P45 Setting not needed P45 Setting not needed P45 Setting not needed P46 Setting not needed P46 Setting not needed P70 Setting impossible P71 Setting impossible P72 Setting impossible P73 Setting impossible P74 Setting impossible P75 Setting impossible P76 Setting impossible P77 Setting impossible P78 Setting impossible P79 Setting impossible P710 Setting impossible I O Input Inpu...

Page 176: ...Setting impossible P712 Setting impossible P713 Setting impossible P714 Setting impossible P715 Setting impossible P80 Setting impossible P780 Setting impossible P90 Setting not needed P91 Setting not needed P92 Setting not needed P92 Setting not needed P93 Setting not needed P93 Setting not needed P94 Setting not needed P94 Setting not needed P95 Setting not needed P95 Setting not needed P96 Sett...

Page 177: ...M913 Setting not needed PM914 Setting not needed PM914 Setting not needed PM915 Setting not needed PM915 Setting not needed Pnx Bit of Pn Register P99 Setting not needed P99 Setting not needed P910 Setting not needed P910 Setting not needed P911 Setting not needed P911 Setting not needed P912 Setting not needed P912 Setting not needed P913 Setting not needed P913 Setting not needed P914 Setting no...

Page 178: ...etting not needed PMCT4 Setting not needed PMCT6 Setting not needed Pnx Bit of Pn Register PCM0 Setting not needed PCM1 Setting not needed PCM2 Setting not needed PCM3 Setting not needed PCS0 Setting not needed PCS1 Setting not needed PCS2 Setting not needed PCS3 Setting not needed PCT0 Setting not needed PCT1 Setting not needed PCT4 Setting not needed PCT6 Setting not needed I O Input Output Outp...

Page 179: ...ded PMDL14 Setting not needed PMDL15 Setting not needed Pnx Bit of Pn Register PDH0 Setting not needed PDH1 Setting not needed PDH2 Setting not needed PDH3 Setting not needed PDH4 Setting not needed PDH5 Setting not needed PDH6 Setting not needed PDH7 Setting not needed PDL0 Setting not needed PDL1 Setting not needed PDL2 Setting not needed PDL3 Setting not needed PDL4 Setting not needed PDL5 Sett...

Page 180: ...f the output latch of a pin set in the input mode in addition to the bit to be manipulated become undefined 4 4 2 Reading data from I O port 1 In output mode The contents of the output latch can be read by using a transfer instruction The contents of the output latch do not change 2 In input mode The status of the pin can be read by using a transfer instruction The contents of the output latch do ...

Page 181: ...electable for each area selected by chip select function External wait function using WAIT pin Idle state function Bus hold function 5 2 Bus Control Pins The pins used to connect an external device are listed in the table below Table 5 1 Bus Control Pins Multiplexed Bus Bus Control Pin Alternate Function Pin I O Function AD0 to AD15 PDL0 to PDL15 I O Address data bus A16 to A23Note PDH0 to PDH7 Ou...

Page 182: ...t Read strobe signal HLDRQ PCM3 Input HLDAK PCM2 Output Bus hold control Note A16 to A21 in the V850ES SA2 5 2 1 Pin status when internal ROM internal RAM or peripheral I O is accessed Table 5 3 Pin Status When Internal ROM Internal RAM or Peripheral I O Is Accessed Access Destination Address Bus Data Bus Control Signal D0 to D15 Undefined Hi Z Inactive A0 to A15 Undefined Hi Z Inactive A16 to A23...

Page 183: ...ternal peripheral I O area 4 KB Use prohibited External memory area 4 MB External memory area 2 MB 2 MB CS0 CS1 CS2 CS3 3 F F F F F F H 3 F E C 0 0 0 H 3 F E B F F F H 1 0 0 0 0 0 0 H 0 F F F F F F H 0 8 0 0 0 0 0 H 0 7 F F F F F H 0 4 0 0 0 0 0 H 0 3 F F F F F H 0 2 0 0 0 0 0 H 0 1 F F F F F H 0 0 0 0 0 0 0 H 3 F F F F F F H 3 F F F 0 0 0 H 3 F F E F F F H 3 F F B 0 0 0 H 3 F F A F F F H 3 F E C ...

Page 184: ...FFFFFH 2 MB CS1 0200000H to 03FFFFFH 2 MB 0200000H to 03FFFFFH 2 MB CS2 0400000H to 07FFFFFH 4 MB 0400000H to 07FFFFFH 4 MB CS3 0800000H to 0BFFFFFH 4 MB 0800000H to 0FFFFFFH 8 MB 5 4 External Bus Interface Mode Control Function The V850ES SA2 and V850ES SA3 include the following two external bus interface modes Multiplexed bus mode Separate bus mode These two modes can be selected by using the ex...

Page 185: ...external memory area of the V850ES SA2 0100000H to 0BFFFFFH is selected by CS0 to CS3 The external memory area of the V850ES SA3 0100000H to 0FFFFFFH is selected by CS0 to CS3 1 Bus size configuration register BSC This register can be read or written in 16 bit units Caution Write to the BSC register after reset and then do not change the set values Also do not access an external memory area other ...

Page 186: ...ribed below All data is accessed starting from the lower side The V850ES SA2 and V850ES SA3 support only the little endian format Figure 5 2 Little Endian Address in Word 000BH 000AH 0009H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 31 24 23 16 15 8 7 0 1 Byte access 8 bits a 16 bit data bus width 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External da...

Page 187: ... 0 15 8 15 8 7 0 7 0 15 8 15 8 2n 2 Halfword data External data bus 2n Address Halfword data External data bus Address 2n 1 b 8 bit data bus width 1 Access to even address 2n 2 Access to odd address 2n 1 First access Second access 7 0 7 0 15 8 Address 7 0 7 0 15 8 2n 1 Address 2n Halfword data External data bus Halfword data External data bus First access Second access 7 0 7 0 15 8 7 0 7 0 15 8 2n...

Page 188: ... 16 31 24 7 0 7 0 15 8 4n 2 15 8 4n 3 23 16 31 24 Word data External data bus Address Word data External data bus Address 2 Access to address 4n 1 First access Second access Third access 7 0 7 0 15 8 15 8 4n 1 23 16 31 24 7 0 7 0 15 8 4n 2 15 8 4n 3 23 16 31 24 7 0 7 0 15 8 4n 4 15 8 23 16 31 24 Word data External data bus Address Word data External data bus Address Word data External data bus Add...

Page 189: ... 7 0 7 0 15 8 4n 4 15 8 4n 5 23 16 31 24 Word data External data bus Address Word data External data bus Address 4 Access to address 4n 3 First access Second access Third access 7 0 7 0 15 8 15 8 4n 3 23 16 31 24 7 0 7 0 15 8 4n 4 15 8 4n 5 23 16 31 24 7 0 7 0 15 8 4n 6 15 8 23 16 31 24 Word data External data bus Address Word data External data bus Address Word data External data bus Address ...

Page 190: ...31 24 Word data External data bus Address Word data External data bus Address Word data External data bus Address Word data External data bus Address 2 Access to address 4n 1 First access Second access Third access Fourth access 7 0 7 0 15 8 4n 1 23 16 31 24 7 0 7 0 4n 2 15 8 23 16 31 24 7 0 7 0 4n 3 15 8 23 16 31 24 7 0 7 0 4n 4 15 8 23 16 31 24 Word data External data bus Address Word data Exter...

Page 191: ... data External data bus Address 7 0 7 0 15 8 4n 2 23 16 31 24 7 0 7 0 4n 3 15 8 23 16 31 24 7 0 7 0 4n 4 15 8 23 16 31 24 7 0 7 0 4n 5 15 8 23 16 31 24 4 Access to address 4n 3 First access Second access Third access Fourth access 7 0 7 0 15 8 4n 3 23 16 31 24 7 0 7 0 4n 4 15 8 23 16 31 24 7 0 7 0 4n 5 15 8 23 16 31 24 7 0 7 0 4n 6 15 8 23 16 31 24 Word data External data bus Address Word data Ext...

Page 192: ...d without a wait state The internal peripheral I O area is also not subject to programmable wait and only wait control from each peripheral function is performed 2 Write to the DWC0 register after reset and then do not change the set values Also do not access an external memory area other than the one for this initialization routine until the initial settings of the DWC0 register are complete Howe...

Page 193: ...tely after the T1 and TW states of the bus cycle If the setup hold time of the sampling timing is not satisfied a wait state is inserted in the next state or not inserted at all 5 6 3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles contr...

Page 194: ...tate is extended by 1 clock If an address hold wait is inserted it seems that the low clock period of T1 state is extended by 1 clock 1 Address wait control register AWC This register can be read or written in 16 bit units After reset FFFFH R W Address FFFFF488H 1 AHW3 AHWn 0 1 Not inserted Inserted AWC 1 ASW3 1 AHW2 1 ASW2 1 AHW1 1 ASW1 1 AHW0 1 ASW0 8 9 10 11 12 13 Specifies insertion of address...

Page 195: ...e is inserted for all the areas immediately after system reset 1 Bus cycle control register BCC This register can be read or written in 16 bit units Cautions 1 The internal ROM internal RAM and internal peripheral I O areas are not subject to idle state insertion 2 Write to the BCC register after reset and then do not change the set values Also do not access an external memory area other than the ...

Page 196: ...he bus hold status is indicated by assertion of the HLDAK pin low level The bus hold function enables the configuration multi processor type systems in which two or more bus masters exist Note that the bus hold request is not acknowledged during a multiple access cycle initiated by the bus sizing function or a bit manipulation instruction Status Data Bus Width Access Type Timing in Which Bus Hold ...

Page 197: ...st inhibition released 9 Bus cycle starts Normal status Bus hold status Normal status HLDAK output HLDRQ input 1 2 5 3 4 7 8 9 6 5 8 3 Operation in power save mode Because the internal system clock is stopped in the software STOP and IDLE modes the bus hold status is not entered even if the HLDRQ pin is asserted In the HALT mode the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted ...

Page 198: ... If a branch instruction exists at the upper limit of the internal RAM area a prefetch operation straddling over the internal peripheral I O area invalid fetch does not occur 2 Instruction execution to the external memory area cannot be continued without a branch from the internal ROM area to the external memory area 5 10 2 Data space The V850ES SA2 and V850ES SA3 have an address misalign function...

Page 199: ...W TW T3 TI T1 Programmable wait External wait Idle state CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 RD 8 bit access AD15 to AD8 AD7 to AD0 Odd address Active Even address Active Figure 5 5 Multiplexed Bus Read Timing Bus Size 8 Bits A1 A2 A3 D1 D2 A3 A2 A1 T1 T2 T3 T1 T2 TW TW T3 TI T1 Programmable wait External wait Idle state CLKOUT A23 to A16 AD15 to AD8 ASTB CS3 to CS0 WAIT AD7 to AD0 ...

Page 200: ...3 T1 Programmable wait External wait CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 WR1 WR0 WR1 WR0 01 10 8 bit access AD15 to AD8 AD7 to AD0 Odd address Active Even address Active Figure 5 7 Multiplexed Bus Write Timing Bus Size 8 Bits A1 11 10 11 11 10 11 A2 A3 D1 D2 A3 A2 A1 T2 T3 T1 T1 T2 TW TW T3 T1 Programmable wait External wait CLKOUT A23 to A16 AD15 to AD8 ASTB CS3 to CS0 WAIT AD7 to ...

Page 201: ...igure 5 8 Multiplexed Bus Hold Timing Bus Size 16 Bits 16 Bit Access T1 A1 A1 A2 A2 T2 T3 TH TH TH TH TH TH T1 T2 T3 D1 D2 Hi Z Hi Z Hi Z Hi Z Hi Z CLKOUT HLDRQ HLDAK A23 to A16 ASTB CS3 to CS0 AD15 to AD0 RD Remark For the status of each pin during bus hold refer to Table 2 3 ...

Page 202: ...2 TI T1 D3 D2 Programmable wait External wait Idle state D1 CLKOUT A0 to A23 CS0 to CS3 WAIT AD0 to AD15 RD 8 bit access AD15 to AD8 AD7 to AD0 Odd address Active Even address Active Figure 5 10 Separate Bus Read Timing Bus Size 8 Bits T1 A1 A2 A3 T2 T1 TW TW T2 T2 TI T1 D3 D2 Programmable wait External wait Idle state D1 CLKOUT A0 to A23 CS0 to CS3 WAIT AD0 to AD15 RD ...

Page 203: ...s 16 Bit Access T1 A1 A2 A3 T2 T1 TW TW T2 T1 T2 D3 D2 Programmable wait External wait D1 CLKOUT A0 to A23 CS0 to CS3 WAIT AD0 to AD7 WR0 WR1 Figure 5 12 Separate Bus Write Timing Bus Size 8 Bits T1 A1 A2 A3 T2 T1 TW TW T2 T1 T2 D3 D2 Programmable wait External wait D1 10 CLKOUT A0 to A23 CS0 to CS3 WAIT AD0 to AD7 WR0 WR1 10 10 ...

Page 204: ...AD0 to AD7 WR0 WR1 CS0 to CS3 Figure 5 14 Address Wait Timing Separate Bus Read Bus Size 16 Bits 16 Bit Access a Without wait inserted b With wait inserted TASW T1 TAHW T2 CLKOUT ASTB A0 to A23 CS0 to CS3 WAIT A0 to A16 RD D1 A1 T1 T2 CLKOUT ASTB A0 to A23 CS0 to CS3 WAIT A0 to A16 RD D1 A1 Remarks 1 TASW address setup wait Image of extended high level width of T1 state 2 TAHW address hold wait Im...

Page 205: ...he features of the clock generation function are as follows Main clock oscillator fX 2 to 17 MHz at 2 2 to 2 7 V operation Subclock oscillator fXT 32 768 kHz Generation of internal system clock fXX Seven steps fX fX 2 fX 4 fX 8 fX 16 fX 32 fXT Generation of peripheral clock Clock output function ...

Page 206: ...control HALT control HALT mode CPU clock A D converter RTC clock Peripheral clock WDT clock Internal system clock Prescaler 3 Main clock oscillator Main clock oscillator stop control XT1 XT2 CLKOUT X1 X2 IDLE Selector fX 32 fX 16 fX 8 fX 4 fX 2 fX fCPU fXX fXT fXT fX fX 512 fX 26 to fX 29 fXT fXT fX fX fXW Remark fX Main clock frequency fXT Subclock frequency fCPU CPU clock frequency fXX Internal ...

Page 207: ... to fX 512 to be supplied to the internal peripheral functions The clock is supplied to the following blocks TM0 to TM5 CSI0 to CSI4 UART0 UART1 I 2 C ADC DAC 5 Prescaler 2 This circuit divides the main clock fX The clock generated by prescaler 2 fX to fX 32 is supplied to the selector that generates the internal system clock fXX fXX is the clock that is supplied to the CPU INTC DMAC and ROMC bloc...

Page 208: ...828H Main clock operation Subclock operation CLS 0 1 Status of CPU clock fCPU fX fX 2 fX 4 fX 8 fX 16 fX 32 Setting prohibited fXT subclock 32 768 kHz CK2 0 0 0 0 1 1 1 X Selects clock fXX fCPU CK1 0 0 1 1 0 0 1 X CK0 0 1 0 1 0 1 X X CK3 0 0 0 0 0 0 0 1 Even if the MCK bit is set to 1 while the system is operating with the main clock as the CPU clock the operation of the main system clock does not...

Page 209: ...wing time is required between when the CK3 bit is set and when the subclock operation is started Maximum 1 Subclock frequency Therefore read the CLS bit and confirm that the subclock operation has started 4 MCK 0 Clear MCK to 0 only when stopping the main clock b Example of setting when changing subclock to main clock 1 MCK 1 Oscillation of the main clock is started 2 Software wait Insert wait sta...

Page 210: ...ster that controls the operation status and clock operation in the power save mode It can be read or written in 8 bit or 1 bit units RESET input clears this register to 00H 0 IDLE mode Software STOP mode PSM 0 1 Specifies operation in software standby mode valid when bit 1 STP of the PSC register is set to 1 PSMR 0 0 0 0 0 0 PSM After reset 00H R W Address FFFFF820H Cautions 1 Be sure to clear bit...

Page 211: ... 1 RESET pin input 2 During oscillation stabilization time count 3 HALT mode 4 IDLE mode 5 Software STOP mode 6 Subclock operation mode 7 Sub IDLE mode 8 Backup mode 6 4 2 Clock output function The clock output function allows the CLKOUT pin to output the internal system clock fXX The internal system clock fXX is selected by using the CK2 to CK0 bits of the processor clock control register PCC The...

Page 212: ... clock oscillation Generation of baud rate for count clock of A D converter source clock main clock oscillator Interval timer INTBRG Figure 6 2 Block Diagram of Prescaler 3 Selector fX fX 8 fX 4 fX 2 fX BGCS0 BGCS1 TODIS BGCE 3 bit prescaler 8 bit counter Output control PRSCM PRSCM0 to PRSCM7 Match fBGCS fBRG INTBRG Prescaler mode register WTM Remark fBRG Prescaler 3 clock frequency fX Main clock ...

Page 213: ...o 0 BGCE 0 1 1 TODIS X 0 1 Baud rate output Fixed to 0 Operates Operates Baud rate interrupt signal INTBRG fX fX 2 fX 4 fX 8 10 MHz 100 ns 200 ns 400 ns 800 ns 4 MHz 250 ns 500 ns 1 s 2 s BGCS1 0 0 1 1 BGCS0 0 1 0 1 Selects input clock fBRGS After reset 00H R W Address FFFFF8B0H µ µ Cautions 1 Do not change the values of BGCS1 and BGCS0 during transmission reception 2 Set the PRSM register before ...

Page 214: ...nt clock of watch timer The clock fBRG input to the watch timer can be corrected to 32 768 kHz or equivalent frequency The relationship between the main oscillation clock fX the set value of input clock selection bit BGCSn m the set value of the PRCSM register N and the output clock fBRG is as follows Example Where fX 4 00 MHz m 0 BGCS1 BGCS 0 N 3DH fBRG 32 768 kHz fBRG fX 2 m N 2 Remark fBRG Coun...

Page 215: ...t timer counter Capture compare common registers 2 2 channels Interrupt request sources Capture match interrupt requests 2 2 channels Overflow interrupt requests 1 2 channels Timer counter count clock sources 2 Selection of external pulse input or internal system clock division Either free running mode or overflow stop mode can be selected as the operation mode when the timer counter overflows Tim...

Page 216: ... TO0 S CC01 Read write INTCC01 INTP01 TO0 R TM1 Read INTOVF1 CC10 Read write INTCC10 INTP10 TO1 S TM0 TM1 fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 CC11 Read write INTCC11 INTP11 TO1 R Remark fXX Internal system clock S R Set reset Figure 7 1 Block Diagram of 16 Bit Timer Event Counter RNote Q S Q TMn 16 bits CCn0 CCn1 INTOVFn INTCCn0 INTPn1 fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX ...

Page 217: ...0H 0000H Address After reset 0 TMn performs the count up operations of an internal count clock or external count clock Timer start and stop are controlled by the TMCEn bit of timer mode control register n0 TMCn0 n 0 1 The internal or external count clock is selected by the ETIn bit of timer mode control register n1 TMCn1 n 0 1 a Selection of the external count clock TMn operates as an event counte...

Page 218: ...XX 32 fXX 64 fXX 128 and fXX 256 by the TMCn0 register fXX Internal system clock An overflow interrupt can be generated if the timer overflows Also the timer can be stopped following an overflow by setting the OSTn bit of the TMCn1 register to 1 Caution The count clock cannot be changed while the timer is operating The conditions when the TMn register becomes 0000H are shown below a Asynchronous r...

Page 219: ... timer TMn is synchronized with the capture trigger and the value of TMn is latched in the CCn0 and CCn1 registers capture operation The valid edge of the INTPn0 pin is specified rising falling or both rising and falling edges according to the IESn01 and IESn00 bits of the SESn register and the valid edge of the INTPn1 pin is specified according to the IESn11 and IESn10 bits of the SESn register n...

Page 220: ...reset function The corresponding timer output TOn is set or reset in synchronization with the generation of a match signal n 0 1 The interrupt selection source differs according to the function of the selected register Cautions 1 When writing to capture compare registers n0 and n1 always set the TMCAEn bit to 1 first If the TMCAEn bit is 0 the data that is written will be invalid 2 Write to captur...

Page 221: ...s Overflow occurs OVFn 0 1 TMn register overflow detection TMCn0 n 0 1 CSn2 CSn1 CSn0 0 0 TMCEn TMCAEn 6 5 4 3 2 1 After reset 00H R W Address TMC00 FFFFF606H TMC10 FFFFF616H When TMn has counted up from FFFFH to 0000H the OVFn bit becomes 1 and an overflow interrupt request INTOVFn is generated at the same time However if TMn is cleared to 0000H after a match at FFFFH when the CCn0 register is se...

Page 222: ...nt disabled stops at 0000H and does not operate Counting operation is performed TMCEn 0 1 TMn register operation control When TMCEn 0 the external pulse output TOn becomes inactive the active level of TOn output is set by the ALVn bit of the TMCn1 register When the TMCAEn bit is set to 0 the TMn unit can be asynchronously reset When TMCAEn 0 the TMn unit is in a reset state Therefore to operate TM...

Page 223: ...e registers are compare registers CMSn0 and CMSn1 bits of TMCn1 register 1 n 0 1 1 2 OSTn After the overflow counting continues free running mode After the overflow the timer maintains the value 0000H and counting stops overflow stop mode OSTn 0 1 Setting of operation when TMn register overflows TMCn1 n 0 1 ENTOn ALVn ETIn CCLRn ECLRn CMSn1 CMSn0 7 6 5 4 3 2 1 0 After reset 00H R W Address TMC01 F...

Page 224: ... operation mode selection Clearing is disabled Clearing is enabled if CCn0 and TMn match during a compare operation TMn is cleared CCLRn 0 1 TMn register clear enable disable specification during compare operation Low level High level ALVn 0 1 External pulse output TOn active level specification The initial value of the ALVn bit is 1 Specifies the input clock internal Specifies the external clock ...

Page 225: ...after setting the TMCEn bit of the TMCn0 register to 0 If the SESn register is overwritten during timer operation operation cannot be guaranteed Falling edge Rising edge Setting prohibited Both rising and falling edges TESn1 0 0 1 1 Valid edge of TIn pin TESn0 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges CESn1 0 0 1 1 Valid edge of TCLRn pin CESn0 0 1 0 1 Falli...

Page 226: ...d and the timer output signal TOn can be set or reset Also a capture operation that holds the TMn register count value in the CCn0 or CCn1 register is performed in synchronization with the valid edge that was detected from the external interrupt request input pin as an external trigger The capture value is held until the next capture trigger is generated Caution When using the INTPn0 TIn0 pin as a...

Page 227: ...Also the overflow interrupt INTOVFn is not generated When the TMn register is changed from FFFFH to 0000H because the TMCEn bit changes from 1 to 0 the TMn register is considered to be cleared but the OVFn bit is not set 1 and no INTOVFn interrupt is generated Also timer operation can be stopped after an overflow by setting the OSTn bit of the TMCn1 register to 1 When the timer is stopped due to a...

Page 228: ...an external trigger capture trigger The TMn count value during counting is captured and held in the capture register in synchronization with that capture trigger signal The capture register value is held until the next capture trigger is generated Also an interrupt request INTCCn0 or INTCCn1 is generated by INTPn0 or INTPn1 signal input The valid edge of the capture trigger is set by valid edge se...

Page 229: ...ual U15905EJ1V0UD 229 Figure 7 5 TM1 Capture Operation Example When Both Edges Are Specified TM1 Count start TMCE1 1 Overflow OVF1 1 D0 D1 D2 D0 D1 D2 Interrupt request INTP11 TM1 count values Capture register CC11 Remark D0 to D2 TM1 register count values ...

Page 230: ...ntroller The match signal causes the timer output pin TOn to change and an interrupt request signal INTCCnn to be generated at the same time If the CCn0 or CCn1 registers are set to 0000H the 0000H after the TMn register counts up from FFFFH to 0000H is judged as a match In this case the TMn register value is cleared 0 at the next count timing however this 0000H is not judged as a match Also the 0...

Page 231: ...D 231 Figure 7 7 Compare Operation Example When CCLR1 1 and CC10 Is 0000H 0001H 0000H 0000H 0000H FFFFH TM1 INTOVF1 Count up Compare register CC10 Match detection INTCC10 Remark A match is detected immediately after the count up and the match detection signal is generated ...

Page 232: ...e output level of the TOn pin is reset The output level of the TOn pin can be specified by the TMCn1 register Remark n 0 1 Table 7 2 TOn Output Control TOn Output ETIn ALVn External Pulse Output Output Level 0 0 Disable High level 0 1 Disable Low level 1 0 Enable When the CCn0 register is matched low level When the CCn1 register is matched high level 1 1 Enable When the CCn0 register is matched hi...

Page 233: ...e of the CCn0 register the TMn register is cleared 0000H and an interrupt request signal INTCCn0 is generated at the same time that the count operation resumes Remark n 0 1 Figure 7 9 Contents of Register Settings When 16 Bit Timer Event Counter Is Used as Interval Timer Supply input clocks to internal units Enable count operation 0 0 1 0 1 0 1 1 0 0 1 1 OSTn ENTOn ALVn ETIn CCLRn CMSn1 CMSn0 0 1 ...

Page 234: ...Operation Timing Example 0000H 0001H p 0000H 0001H p p p p p p 0000H 0001H t Count start Interval time Interval time Interval time Count clock TMn register CCn0 register INTCCn0 interrupt Clear Clear Remarks 1 p Setting value of CCn0 register 0000H to FFFFH t Count clock cycle Interval time p 1 t 2 n 0 1 ...

Page 235: ...es counting In this way a PWM signal whose frequency is determined according to the setting of the CSn2 to CSn0 bits of the TMCn0 register can be output When the setting value of the CCn0 register and the setting value of the CCn1 register are the same the TOn output remains inactive and does not change The active level of the TOn output can be set by the ALVn bit of the TMCn1 register Remark n 0 ...

Page 236: ...H Count clock TMn register CCn0 register CCn1 register INTCCn0 interrupt INTCCn1 interrupt TOn output Count start Clear t Remarks 1 p Setting value of CCn0 register 0000H to FFFFH q Setting value of CCn1 register 0000H to FFFFH p q t Count clock cycle PWM cycle 65 536 t 65 536 p q Duty 2 In this example the active level of the TOn output is set to the high level 3 n 0 1 ...

Page 237: ...Cn1 register The active level of the TOn output can be set by the ALVn bit of the TMCn1 register When the setting value of the CCn0 register and the setting value of the CCn1 register are the same the TOn output remains inactive and does not change The active level of the TOn output can be set by the ALVn bit of the TMCn1 register Remark n 0 1 Figure 7 13 Contents of Register Settings When 16 Bit ...

Page 238: ... Count stop Count clock TMn register CCn0 register CCn1 register INTCCn0 interrupt INTCCn1 interrupt TOn output t Remarks 1 p Setting value of CCn0 register 0000H to FFFFH q Setting value of CCn1 register 0000H to FFFFH p q t Count clock cycle 2 In this example the valid edge of the TCLRn input is set to the rising edge and the active level of the TOn output is set to the high level 3 n 0 1 ...

Page 239: ...dge input of the INTPn1 pin is set as the trigger for capturing the TMn register value in the CCn1 register When this value is captured an INTCCn1 interrupt is generated The cycle of signals input to the INTPn0 pin is calculated by obtaining the difference between the TMn register s count value Dx that was captured in the CCn0 register according to the x th valid edge input of the INTPn0 pin and t...

Page 240: ...s Enable count operation 0 0 1 0 1 0 1 0 1 0 1 0 0 OSTn ENTOn ALVn ETIn CCLRn CMSn1 CMSn0 0 1 0 1 0 1 0 1 0 0 1 1 OVFn TMCn0 TMCn1 CSn2 CSn1 CSn0 TMCEn TMCAEn Use CCn0 register as capture register when measuring the cycle of INTPn0 input Use CCn1 register as capture register when measuring the cycle of INTPn1 input Continue counting after TMn register overflows ECLRn Remarks 1 0 1 Set to 0 or 1 as...

Page 241: ...D1 D0 t D3 D2 t 10000H D1 D2 tNote t Count clock TMn register INTPn0 input CCn0 register INTCCn0 interrupt INTOVFn interrupt No overflow Overflow occurs No overflow Clear Count start Note When an overflow occurs once Remarks 1 D0 to D3 TMn register count values t Count clock cycle 2 In this example the valid edge of the INTPn0 input has been set to both edges rising and falling 3 n 0 1 ...

Page 242: ...ter is a TMn reset signal To use TMn first set 1 the TMCAEn bit 5 The analog noise elimination time two cycles of the input clock are required to detect the valid edge of the external interrupt request signal INTPn0 or INTPn1 or the external clock input TIn Therefore edge detection will not be performed normally for changes that are less than the analog noise elimination time two cycles of the inp...

Page 243: ...nt counter alone individual mode 8 bit timer event counter n operates as an 8 bit timer event counter The following functions can be used Interval timer External event counter Square wave output PWM output 2 Mode using cascade connection 16 bit resolution cascade connection mode TM2 and TM3 and TM4 and TM5 can be used as 16 bit timer event counters when they are connected in cascade The following ...

Page 244: ...timer event counter n 8 bit timer event counter n consists of the following hardware n 2 to 5 Table 7 3 Configuration of 8 Bit Timer Event Counter n Item Configuration Timer registers 8 bit timer counters 2 to 5 TM2 to TM5 16 bit timer counters 23 and 45 TM23 TM45 Only when using cascade connection Registers 8 bit timer compare registers 2 to 5 CR2 to CR5 16 bit timer compare registers 23 and 45 C...

Page 245: ... 4 2 8 bit timer compare registers 2 to 5 CR2 to CR5 The CRn register can be read and written by an 8 bit memory manipulation instruction In a mode other than the PWM mode the value set to the CRn register is always compared to the count value of 8 bit counter n TMn and if the two values match an interrupt request signal INTTMn is generated In the PWM mode TMn register overflow causes the TOn pin ...

Page 246: ... the valid edge of the TIn pin input The TCLn register is set by an 8 bit memory manipulation instruction RESET input clears this register to 00H Falling edge of TIn Rising edge of TIn fXX 4 fXX 8 fXX 16 fXX 32 fXX 128 fXX 512 Count clock selection TCLn2 0 0 0 0 1 1 1 1 TCLn1 0 0 1 1 0 0 1 1 TCLn0 0 1 0 1 0 1 0 1 17 MHz 13 5 MHz 235 ns 470 ns 941 ns 1 88 s 7 53 s 30 1 s 296 ns 593 ns 1 19 s 2 37 s...

Page 247: ...0 1 0 1 0 1 0 1 17 MHz 13 5 MHz 235 ns 470 ns 941 ns 1 88 s 7 53 s 15 1 s 296 ns 593 ns 1 19 s 2 37 s 9 48 s 19 0 s Clock fXX 0 TCLn n 4 5 0 0 0 0 TCLn2 TCLn1 TCLn0 After reset 00H R W Address TCL4 FFFFF654H TCL5 FFFFF655H 7 6 5 4 3 2 1 0 µ µ µ µ µ µ µ Caution Before overwriting the TCLn register with different data stop the timer operation Remark When TCL4 and TCL5 are connected in cascade the TC...

Page 248: ...ounters 2 to 5 TM2 toTM5 Selects the operation mode of the TMn register Selects the individual mode or cascade connection mode Sets the status of the timer output flip flop Controls the timer output flip flop or selects the active level in the PWM free running mode Controls timer output The TMCn register is set by an 8 bit or 1 bit memory manipulation instruction RESET input clears these registers...

Page 249: ... TMC3 FFFFF646H TMC3 FFFFF647H Disable inversion operation Enable inversion operation High active Low active TMCn1 0 1 Other than PWM free running mode TMCn6 0 Controls timer F F PWM free running mode TMCn6 1 Selects active level Disable output TOn pin is low level Enable output TOEn 0 1 Timer output control 7 6 5 4 3 2 1 0 TMC4 FFFFF656H TMC5 FFFFF657H Note Bit 4 of the TMC2 and TMC4 registers is...

Page 250: ...er Compare value N TMCn register Stops count operation and selects the mode in which clear start occurs on a match between the TMn register and CRn register TMCn register 0000xxx0B don t care 2 When the TCEn bit of the TMCn register is set to 1 the count operation starts 3 When the values of the TMn register and CRn register match INTTMn is generated TMn register is cleared to 00H 4 Then INTTMn is...

Page 251: ...ion 2 2 When CRn register 00H t Interval time 00H 00H 00H 00H 00H Count clock TMn count value CRn TCEn INTTMn Remark n 2 to 5 When CRn register FFH t 01H 00H FEH FFH 00H FEH FFH 00H FFH FFH FFH Count clock TMn count value CRn TCEn INTTMn TOn Interval time Interrupt acknowledgment Interrupt acknowledgment Remark n 2 to 5 ...

Page 252: ...of TIn pin TCLn 01H CRn register Compare value N TMCn register Stops count operation selects the mode in which clear start occurs on a match between the TMn register and CRn register disables timer output F F inversion operation and disables timer output TMCn register 0000xx00B don t care 2 When the TCEn bit of the TMCn register is set to 1 the counter counts the number of pulses input from TIn 3 ...

Page 253: ...CRn register Compare value N TMCn register Stops count operation selects the mode in which clear start occurs on a match between the TMn register and CRn register LVSn LVRn Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Enables timer output F F inversion operation and enables timer output TMCn register 00001011B or 00000111B 2 When the TCEn bit of the TMCn register is s...

Page 254: ...D 254 Figure 7 20 Timing of Square Wave Output Operation 00H 01H 02H N 1 N 01H 02H N N 00H Count clock CRn TOn TMn count value INTTMn TCEn Count start 00H N 1 Note The initial value of the TOn output can be set using the LVSn and LVRn bits of the TMCn register Remark n 0 1 ...

Page 255: ...ter TCLn register Selects the count clock t CRn register Compare value N TMCn register Stops count operation selects PWM mode and leave timer output F F unchanged TMCn1 Active Level Selection 0 Active high 1 Active low Timer output enabled TMCn register 01000001B or 01000011B 2 When the TCEn bit of the TMCn register is set to 1 counting starts PWM output operation 1 When counting starts PWM output...

Page 256: ... Inactive level Active level Count clock TMn count value CRn TCEn INTTMn TOn When CRn register 00H 00H N 1N 2 N 00H 00H M 00H FFH 01H 02H 01H 00H FFH 02H 01H Inactive level Inactive level Count clock TMn count value CRn TCEn INTTMn TOn When CRn register FFH 00H N 1N 2 N FFH 00H M 00H FFH 01H 02H 01H 00H FFH 02H 01H Inactive level Inactive level Inactive level Active level Active level Count clock ...

Page 257: ...Rn transition N M M M 1M 2 M M 1M 2 FFH 02H 00H 01H FFH 02H 00H 01H Count clock TMn count value CRn TCEn H INTTMn TOn 2 When the value of the CRn register changes from N to M after the rising edge of the FFH clock The value of the CRn register is reloaded at the second overflow N N 1 N 2 N N N 1 CRn transition N M M N 1 N 2 M M 1M 2 FFH 03H 02H 00H 01H FFH 02H 00H 01H Count clock TMn count value C...

Page 258: ...lue N Lower 8 bits settable from 00H to FFH CR3 register Compare value N Higher 8 bits settable from 00H to FFH TMC2 TMC3 register Selects the mode in which clear start occurs on a match between TM23 register and CR23 register don t care TMC2 register 0000xx00B TMC3 register 0001xx00B 2 Set the TCE3 bit of the TMC3 register to 1 Then set the TCE2 bit of the TMC2 register to 1 to start the count op...

Page 259: ... Figure 7 23 Cascade Connection Mode with 16 Bit Resolution When TM2 and TM3 Are Connected 00H N 1 01H 00H FFH 00H 01H FFH 00H FFH M 1 01H 00H 00H N A 01H 00H 02H M 00H 00H B N N M Interval time Operation ebabled count start Interrupt occurrence level inverted counter cleared Operation stopped Count clock TM2 count value TM3 count value TCE3 INTTM2 TO2 CR3 TCE2 CR2 ...

Page 260: ...0H to FFH TMC2 TMC3 registers Stops count operation selects the clear stop mode entered on a match between the TM23 register and CR23 register disables timer output F F inversion and disables timer output don t care TMC2 register 0000xx00B TMC3 register 0001xx00B 2 Set the TCE3 bit of the TMC3 register to 1 Then set the TCE2 bit of the TMC2 register to 1 and count the number of pulses input from T...

Page 261: ...egister does not have to be set in cascade connection CR2 register Compare value N Lower 8 bits settable from 00H to FFH CR3 register Compare value N Higher 8 bits settable from 00H to FFH TMC2 TCM3 registers Stops count operation selects the mode in which clear start occurs on a match between the TM23 register and CR23 register LVS2 LVR2 Timer Output F F Status Settings 1 0 High level output 0 1 ...

Page 262: ...ng timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started This is because 8 bit timer counter n TMn is started asynchronously to the count pulse Figure 7 24 Start Timing of Timer n 00H Timer start 01H 02H 03H 04H Count pulse TMn count value Remark n 2 to 5 ...

Page 263: ...k fXT is selected The configuration of the real time counter function is shown below Figure 8 1 Block Diagram of Real Time Counter Selector Selector Count enable disable circuit Sub count register SUBC 15 bits Prescaler 3 Second count register SEC 6 bits Internal bus Second count setting register SECB Minute count setting register MIINB Hour count setting register HOURB Day count setting register ...

Page 264: ...6 bit instruction Undefined R SECB Second count setting register 8 bit instruction 00H W MINB Minute count setting register 8 bit instruction 00H W HOURB Hour count setting register 8 bit instruction 00H W DAYB Day count setting register 8 bit instruction 00H W WEEKB Week count setting register 8 16 bit instruction 0000H W 1 RTC control register 0 RTCC0 The RTCC0 register is an 8 bit register that...

Page 265: ...upt request signal every 0 125 second Generates interrupt request signal every 0 25 second Generates interrupt request signal every 0 5 second Generates interrupt request signal every 1 second Generates interrupt request signal every 1 minute Generates interrupt request signal every 1 hour Generates interrupt request signal every 1 day Setting prohibited INTS3 0 0 0 0 0 0 0 0 1 1 1 Specifies inter...

Page 266: ...s 8 bit register uses a value of 0 to 59 decimal to indicate the count value in seconds This register is read only in 8 bit units This register is not initialized by RESET input or when RTCE 0 SEC After reset Undefined R Address FFFFF6E4H 0 0 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 0 1 2 3 4 5 6 7 5 Second count setting register SECB This is an 8 bit register for setting the second count This register is re...

Page 267: ... register for setting the minute count This register is read only in 8 bit units Set a count value in a range of 0 to 59 decimal to this register Do not set a count value of 60 decimal or greater RESET input clears this register to 00H MINB After reset 00H W Address FFFFF6EBH 0 0 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 0 1 2 3 4 5 6 7 8 Hour count register HOUR This 8 bit register uses a value of 0 to 23 de...

Page 268: ...Day count register DAY This 8 bit register used a value of 0 to 6 decimal to indicate the count value in days This register is read only in 8 bit units This register is not initialized by RESET input or when RTCE 0 DAY After reset Undefined R Address FFFFF6E7H 0 0 0 0 0 DAY2 DAY1 DAY0 0 1 2 3 4 5 6 7 11 Day count setting register DAYB This is an 8 bit register for setting the day count This regist...

Page 269: ...gister is not initialized by RESET input or when RTCE 0 WEEK After reset Undefined R Address FFFFF6E8H 0000 WEEK11 to WEEK0 0 15 12 11 13 Week count setting register WEEKB This is a 16 bit register for setting the week count This register is read only in 8 bit or 16 bit units Set a count value in a range of 0 to 4 095 decimal to this register RESET input clears this register to 0000H WEEKB After r...

Page 270: ... registers at all once and each count register starts counting up 5 Each time a count register overflows the higher count register starts counting up 6 At the clock after the one at which the overflow conditions of all the count registers have been satisfied all the count registers are cleared to 0 The INTROV signal is asserted active for the duration of one cycle of the real time count clock afte...

Page 271: ...otes 1 When the reset signal is input the CKS bit of RTC control register 0 RTCC0 is cleared to 0 Therefore the real time counter operates with the subclock fXT Note the following points To continue the real time counter operation even during the reset period select fXT CKS 0 as the count clock If the prescaler 3 clock fBRG CKS 1 is selected the count clock is changed to fXT CKS 0 by the reset inp...

Page 272: ... the values of all the count registers this may be omitted 3 Write a value to one of the count setting registers Write the value read in 2 to the other count setting registers 4 Set RTCE to 1 The values of the count setting registers will be transferred to the count registers and the real time counter will start counting after 2 or 3 count clocks 5 To change the interrupt request signal generation...

Page 273: ...listed operation modes Generation of non maskable interrupt request signal INTWDT upon overflow of watchdog timer Generation of system reset signal upon overflow of watchdog timer Generation of maskable interrupt request signal INTWDTM upon overflow of interval timer Securing of oscillation stabilization time for main system clock Remark Select whether to use the watchdog timer in the watchdog tim...

Page 274: ...fXW fXW 213 fXW 212 fXW 211 fXW 210 fXW 29 fXW 28 fXW 27 fXW 26 fXW 25 Selector OVF INTWDTM INTWDT WDTRES OSTOVF Remark INTWDTM Request signal for maskable interrupt through WDT overflow INTWDT Request signal for non maskable interrupt through WDT overflow WDTRES Reset signal through WDT overflow OSTOVF Oscillation stabilization timer overflow signal OSCMD Oscillation stabilization timer mode sign...

Page 275: ...abilization time selection register OSTS This register selects the oscillation stabilization time following reset or release of the stop mode The OSTS register is set by an 8 bit or 1 bit memory manipulation instruction RESET input sets OSTS to 01H 0 OSTS 0 0 0 0 OSTS2 OSTS1 OSTS0 214 fX 216 fX 217 fX 218 fX 219 fX 220 fX 221 fX 222 fX OSTS2 0 0 0 0 1 1 1 1 Selection of oscillation stabilization t...

Page 276: ...WDCS 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 0 0 0 0 1 1 1 1 Overflow time of watchdog timer interval timer WDCS1 0 0 1 1 0 0 1 1 WDCS0 0 1 0 1 0 1 0 1 After reset 00H R W Address FFFF6C1H 214 fX 215 fX 216 fX 217 fX 218 fX 219 fX 220 fX 222 fX 13 5 MHz 8 MHz 2 048 ms 4 096 ms 8 192 ms 16 38 ms 32 77 ms 65 54 ms 131 1 ms 524 3 ms 17 MHz 964 s 1 928 ms 3 855 ms 7 710 ms 15 42 ms 30 84 ms 61 68 ms 246 7 ms ...

Page 277: ...ection of watchdog timer operation modeNote 1 WDTM 0 0 WDTM4 WDTM3 0 0 0 After reset 00H R W Address FFFFF6C2H Interval timer mode Upon overflow maskable interrupt INTWDTM is generated Watchdog timer mode 1 Upon overflow non maskable interrupt INTWDT is generated Watchdog timer mode 2 Upon overflow reset operation WDTRES is started WDTM4 0 0 1 1 WDTM3 0 1 0 1 Selection of watchdog timer operation ...

Page 278: ... bit WDTM3 of the WDTM register The count operation of the watchdog timer stops in the software STOP mode and IDLE mode Therefore set the RUN bit to 1 before the software STOP mode or IDLE mode is entered in order to clear the watchdog timer Because the watchdog timer operates in the HALT mode do not use the watchdog timer when using the HALT mode Caution Once the WDTM4 bit is cleared to 0 thereby...

Page 279: ...e HALT mode but it stops operating in the software STOP mode and the IDLE mode Therefore set the RUN bit of the WDTM register to 1 before the software STOP mode or IDLE mode is entered in order to clear the interval timer Cautions 1 Once the WDTM4 bit is set to 1 thereby selecting the watchdog timer mode the interval timer mode is not entered as long as RESET is not input 2 When the subclock is se...

Page 280: ...ms 262 1 ms 524 3 ms 17 MHz Setting prohibited 3 855 ms 7 710 ms 15 42 ms 30 84 ms 61 68 ms 123 4 ms 246 7 ms Setting prohibited 4 855 ms 9 709 ms 19 42 ms 38 84 ms 77 67 ms 155 3 ms 310 7 ms fX After reset 04H R W Address FFFFF6C0H Cautions 1 The wait time following release of the software STOP mode does not include the time until the clock oscillation starts a in the figure below following relea...

Page 281: ... INTAD Analog input side C array Reference side C array Controller Successive approximation register SAR A D conversion result register ADCR Selector ADS0 to ADS3 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12Note ANI13Note ANI14Note ANI15Note 0 ...

Page 282: ...rter Comparator Power fail comparison threshold register PFT Selector Selector ADS0 to ADS3 PFCM PFEN INTAD ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12Note ANI13Note ANI14Note ANI15Note 0 ...

Page 283: ... 9 4 1 4 0 6 2 6 96 96 4 3 7 9 7 6 2 1 2 96 1 6 96 96 6 96 0 1 0 1 2 0 0 0 3 1 1 1 0 1 1 0 2 1 0 0 3 1 0 0 1 7 96 7 6 7 4 5 0 1 ...

Page 284: ... 4 6 7 6 7 8 9 9 6 Note 1 Note 2 0 0 9 9 6 1 1 0 1 9 0 0 0 6 7 0 0 0 0 0 0 0 1 1 1 0 0 0 0 3 1 6 7 6 7 ...

Page 285: ... 6 7 ...

Page 286: ... 1 1 FR2 0 1 0 1 19 clocks Setting prohibited Setting prohibited 33 clocks Number of A D conversion clocks FR1 0 0 1 1 FR0 0 1 0 1 fXX 16 fXX 8 fXX 4 Clock of prescaler 3 fBRG A D conversion clock After reset 00H R W Address FFFFF200H 760 76 4 5 5 8 4 760 76 5 5 5 4 660 76 5 6A 7 6A 9B 6 9 6 99 6A A9 6 7 6 9 7 1 6 2 ...

Page 287: ...5 8 D CC 5 0 D CC 5 D CC 5 D 0 E CC 8 µ µ 0 µ CC 0 µ µ 81 µ 81 CC µ 0 µ CC µ E µ 0 8 µ µ CC 0 µ 11 µ 1E CC 00 µ 0 µ 0 CC 11 µ 11 CC E µ µ 3 6 5 6 9 5 6 7 6 6 5 6 9 5 6 7 6 0 0 0 0 1 0 1 1 8 6 6 µ µ µ µ 8 7 4 6 µ µ µ µ 0 1 8 ...

Page 288: ...ANI12Note ANI13Note ANI14Note ANI15Note Setting prohibited ADS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Specification of analog input channel After reset 00H R W Address FFFFF201H Other than above 0 ...

Page 289: ...l comparison Selection of power fail comparison enable disable PFM PFCM 0 0 0 0 0 0 PFCM 0 1 Generates interrupt request signal INTAD when ADCR PFT Generates interrupt request signal INTAD when ADCR PFT Selection of power fail comparison mode After reset 00H R W Address FFFFF202H ...

Page 290: ... 4 4 9 96 7 7 9 7 4 4 7 7 9 7 6 7 79 3 96 7 96 F 7 7 5 2 2 2 Conversion operation ADCR PFT INTAD ANI0 80H 80H 7FH 80H ANI0 ANI0 ANI0 Note 2 ...

Page 291: ...n time 20 µs max AVREF1 2 2 to 2 7 V Analog output voltage AVREF1 m 256 m 0 to 255 value set to DACSn register Operation modes Normal mode real time output mode Remark n 0 1 The D A converter configuration is shown below Figure 11 1 Block Diagram of D A Converter DACS0 R string resistor R string resistor DACS1 ANO0 ANO1 DACE0 DACE1 DACS0 write DAMD0 INTTM2 DACS1 write DAMD1 INTTM3 AVREF1 AVSS ...

Page 292: ... DACS0 and DACS1 1 D A converter mode register DAM This register controls the operation of the D A converter DAM is set by an 8 bit or 1 bit memory manipulation instruction RESET input clears DAM to 00H 0 Normal mode Real time output modeNote DAMDn 0 1 Selection of D A converter operation mode n 0 1 DAM 0 0 0 DAMD1 DACE1 DAMD0 DACE0 After reset 00H R W Address FFFFF284H Disables operation Enables ...

Page 293: ...ins These registers are set by an 8 bit memory manipulation instruction RESET input clears DACS0 and DACS1 to 00H DA7 DACSn DA6 DA5 DA4 DA3 DA2 DA1 DA0 After reset 00H R W Address DACS0 FFFFF280H DACS1 FFFFF282H Caution In the real time output mode DAMDn bit 1 set the DACSn register before the INTTM2 INTTM3 signals are generated D A conversion starts when the INTTM2 INTTM3 signals are generated Re...

Page 294: ... next D A conversion is performed Remark n 0 1 11 4 2 Operation in real time output mode D A conversion is performed using the interrupt request signals INTTM2 and INTTM3 of 8 bit timer event counters 2 and 3 TM2 and TM3 as triggers The setting method is described below 1 Set the DAMDn bit of the DAM register to 1 real time output mode 2 Set the analog voltage value to be output to the ANOn pin to...

Page 295: ...1 pins as port pins make sure that their input level does not change much 4 Make sure that VDD EVDD AVDD AVREF1 2 2 to 2 7 V If this range is exceeded the operation is not guaranteed 5 Apply power to AVDD at the same timing as VDD 6 No current can be output from the ANOn pin n 0 1 because the output impedance of the D A converter is high When connecting a resistor of 5 MΩ or less insert a JFET inp...

Page 296: ...locked serial interface CSIn 4 channels V850ES SA2 5 channels V850ES SA3 3 I 2 C bus interface I 2 C Note 1 channel UARTm in which one byte of serial data is transmitted received following a start bit supports full duplex communication CSIn performs data transfer using three types of signals a serial clock SCKn serial input SIn and serial output SOn 3 wire serial I O I 2 C transfers 8 bit data wit...

Page 297: ...register 3 PFC3 refer to 4 3 3 Port 3 Caution CSI1 or UART0 transmission reception operations are not guaranteed if the mode is changed during transmission or reception Be sure to disable the operation of the unit that is not used Figure 12 1 Selecting CSI1 or UART0 Mode 7 0 PMC3 6 0 5 0 4 0 3 0 2 PMC32 1 PMC31 0 PMC30 7 0 PFC3 6 0 5 0 4 0 3 0 2 0 1 PFC31 0 PFC30 After reset 00H R W Address FFFFF4...

Page 298: ...ons 1 CSI0 or I 2 C transmission reception operations are not guaranteed if the mode is changed during transmission or reception Be sure to disable the operation of the unit that is not used 2 I 2 C µ µ µ µPD703201Y 703204Y 70F3201Y and 70F3204Y only Figure 12 2 Selecting CSI0 or I 2 C Mode 7 0 PMC4 6 PMC46 5 PMC45 4 PMC44 3 PMC43 2 PMC42 1 PMC41 0 PMC40 7 0 PFC4 6 PFC46 5 0 4 PFC44 3 0 2 PFC42 1 ...

Page 299: ...s 3 types Reception error interrupt INTSREn Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSRn Interrupt is generated when receive data is transferred from the shift register to receive buffer register n after serial transfer is completed during a reception enabled state Transmission completion interrupt INTSTn Interrupt ...

Page 300: ...of TXBn data and the transmit shift register data flag which indicates whether transmission is in progress 4 Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register A check for parity errors is also performed during a receive operation and if an error is detected a value corresponding to the error contents is set in the ASISn register ...

Page 301: ...ntrol parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXBn register according to the contents that were set in the ASIMn register Figure 12 3 Asynchronous Serial Interface n Block Diagram Parity Framing Overrun Internal bus Asynchronous serial interface mode register n ASIMn Receive buffer register n RXBn Receive shift regis...

Page 302: ...Stops clock supply to UARTn 1 Supplies clock to UARTn If UARTCAEn 0 UARTn is asynchronously reset If UARTCAEn 0 UARTn is reset To operate UARTn first set UARTCAEn to 1 If the UARTCAEn bit is changed from 1 to 0 all the registers of UARTn are initialized To set UARTCAEn to 1 again be sure to re set the registers of UARTn The output of the TXDn pin goes high when transmission is disabled regardless ...

Page 303: ...ceive shift operation starts synchronized with the detection of the start bit and when the reception of one frame is completed the contents of the receive shift register are transferred to the RXBn register A reception completion interrupt INTSRn is also generated in synchronization with the transfer to the RXBn register 2 Even parity If the transmit data contains an odd number of bits with the va...

Page 304: ...erformed with a stop bit length of 1 the SL bit setting does not affect receive operations ISRMn Enables disables generation of reception completion interrupt requests when an error occurs 0 Generate a reception error interrupt request INTSREn as an interrupt when an error occurs In this case no reception completion interrupt request INTSRn is generated 1 Generate a reception completion interrupt ...

Page 305: ...e ASISn register are cleared 0 7 0 ASISn 6 0 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn After reset 00H R Address FFFFFA03H FFFFFA13H PEn Status flag that indicates a parity error 0 When the ASIMn register s UARTCAEn and RXEn bits are both set to 0 or when the ASISn register has been read 1 When reception was completed the transmit data parity did not match the parity bit The operation of the PEn bit differs ...

Page 306: ... the ASIMn register s POWERn or TXEn bit is 0 or when data has been transferred to the transmit shift register 1 Data to be transferred next exists in the TXBn register data exists in the TXBn register when the TXBn register has been written to When transmission is performed continuously data should be written to the TXBn register after confirming that this flag is 0 If writing to the TXBn registe...

Page 307: ...to 12 2 5 4 Receive operation If reception is disabled RXEn bit 0 in the ASIMn register the contents of the RXBn register are retained and no processing is performed for transferring data to the RXBn register even when the shift in processing of one frame is completed Also no reception completion interrupt is generated When 7 bits is specified for the data length bits 6 to 0 of the RXBn register a...

Page 308: ...ister the value is ignored The TXBn register data is transferred to the transmit shift register and a transmission completion interrupt request INTSTn is generated synchronized with the completion of the transmission of one frame from the transmit shift register For information about the timing for generating this interrupt request refer to 12 2 5 2 Transmit operation When TXBFn bit 1 in the ASIFn...

Page 309: ...rors explained for the ASISn register Whether a reception error interrupt INTSREn or a reception completion interrupt INTSRn is generated when an error occurs can be specified using the ISRMn bit of the ASIMn register When reception is disabled no reception error interrupt is generated 2 Reception completion interrupt INTSRn When reception is enabled a reception completion interrupt is generated w...

Page 310: ...ts as shown in Figure 12 4 The character bit length within one data frame the type of parity and the stop bit length are specified by asynchronous serial interface mode register n ASIMn Also data is transferred LSB first Figure 12 4 Asynchronous Serial Interface Transmit Receive Data Format 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bits Character bits Start bit 1 bit Character...

Page 311: ...buffer register n TXBn When a transmit operation is started the data in TXBn is transferred to the transmit shift register Then the transmit shift register outputs data to the TXDn pin the transmit data is transferred sequentially starting with the start bit The start bit parity bit and stop bits are added automatically c Transmission interrupt request When the transmit shift register becomes empt...

Page 312: ...al U15905EJ1V0UD 312 Figure 12 5 Asynchronous Serial Interface Transmission Completion Interrupt Timing Start Stop D0 D1 D2 D6 D7 Parity Parity TXDn output INTSTn output Start D0 D1 D2 D6 D7 TXDn output INTSTn output a Stop bit length 1 b Stop bit length 2 Stop ...

Page 313: ...irm that the TXBFn bit is 0 and then write the next transmit data second byte to TXBn register If writing to the TXBn register is performed when the TXBFn bit is 1 transmit data cannot be guaranteed While transmission is being performed continuously whether writing to the TXBn register later is enabled can be judged by confirming the TXSFn bit after the occurrence of a transmission completion inte...

Page 314: ... Set registers Interrupt occurrence Wait for interrupt Required number of transfers performed Write transmit data to TXBn register Write transmit data to TXBn register When reading ASIFn register TXBFn 0 When reading ASIFn register TXSFn 1 When reading ASIFn register TXSFn 0 No No No No Yes Yes Yes Yes End of transmission processing ...

Page 315: ...he ASIFn register simultaneously 11 or 00 may be read Thus whether writing to the TXBn register is enabled or not should be judged only for the TXBFn bit ASIFn Register Transmission Starting Procedure Internal Operation TXBFn TXSFn Set transmission mode 1 Start transmission unit 0 0 Write data 1 1 0 2 Generate start bit Read ASIFn register confirm that TXBFn bit 0 Start data 1 transmission 1 0 0 0...

Page 316: ...top bit Stop bit ASIFn Register Transmission End Procedure Internal Operation TXBFn TXSFn 6 Transmission of data m 2 is in progress 1 1 7 INTSTn interrupt occurs Read ASIFn register confirm that TXBFn bit 0 0 0 1 1 Write data m 8 Generate start bit Start data m 1 transmission Transmission in progress 1 1 9 INTSTn interrupt occurs Read ASIFn register confirm that TXSFn bit 1 There is no write data ...

Page 317: ... The RXDn pin is sampled using the serial clock from baud rate generator n BRGn c Reception completion interrupt When RXEn 1 in the ASIMn register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSRn is generated and the receive data within the receive shift register is transferred to RXBn at the same time Also if an overrun error OVE...

Page 318: ...nd overrun error As a result of data reception the various flags of the ASISn register are set 1 and a reception error interrupt INTSREn or a reception completion interrupt INTSRn is generated at the same time The ISRMn bit of the ASIMn register specifies whether INTSREn or INTSRn is generated The type of error that occurred during reception can be detected by reading the contents of the ASISn reg...

Page 319: ...uring reception b An error occurs during reception INTSRn output Reception completion interrupt INTSREn output Reception error interrupt INTSRn output Reception completion interrupt INTSREn output Reception error interrupt INTSRn does not occur Figure 12 11 When Reception Error Interrupt Is Included in Reception Completion Interrupt INTSRn ISRMn Bit 1 a No error occurs during reception b An error ...

Page 320: ...number is odd b Odd parity i During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd The parity bit value is as follows If the number of bits with the value 1 within the transmit data is odd 0 If the number of bits with the value 1 within the transmit data is even 1 ii During re...

Page 321: ...se and is not delivered to the internal circuit see Figure 12 13 Refer to 12 2 6 1 a Base clock Clock regarding the base clock Also since the circuit is configured as shown in Figure 12 12 internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status Figure 12 12 Noise Filter Circuit RXDn Q Clock In LD_EN Q In Internal signal A Internal signal ...

Page 322: ...n configuration Figure 12 14 Configuration of Baud Rate Generator n BRGn fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1 024 TOm output Clock fCLK Selector UARTCAEn 8 bit counter Match detector Baud rate BRGCn MDL7 to MDL0 1 2 UARTCAEn and TXEn or RXEn CKSRn TPS3 to TPS0 fXX Remark fXX Internal system clock n 0 1 m 4 5 m 4 when n 0 m 5 when n 1 a Base clock Clock When the UART...

Page 323: ...0 bits The clock selected by the TPSn3 to TPSn0 bits becomes the base clock Clock of the transmission reception module Its frequency is referred to as fCLK This register can be read or written in 8 bit units Caution Set the UARTCAEn bit of the ASIMn register to 0 before rewriting the TPSn3 to TPSn0 bits 7 0 CKSRn 6 0 5 0 4 0 3 TPSn3 2 TPSn2 1 TPSn1 0 TPSn0 After reset 00H R W Address FFFFFA06H FFF...

Page 324: ...1 MDLn1 0 MDLn0 After reset FFH R W Address FFFFFA07H FFFFFA17H MD Ln7 MD Ln6 MD Ln5 MD Ln4 MD Ln3 MD Ln2 MD Ln1 MD Ln0 Division value k Serial clock 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fCLK 8 0 0 0 0 1 0 0 1 9 fCLK 9 0 0 0 0 1 0 1 0 10 fCLK 10 1 1 1 1 1 0 1 0 250 fCLK 250 1 1 1 1 1 0 1 1 251 fCLK 251 1 1 1 1 1 1 0 0 252 fCLK 252 1 1 1 1 1 1 0 1 253 fCLK 253 1 1 1 1 1 1 1 0 254 fCLK 254...

Page 325: ... formula 100 1 rate baud normal rate baud Desired error with rate baud rate baud Actual Error Cautions 1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable baud rate range described in 4 Allowable baud rate range during reception Example Base clock freq...

Page 326: ...16 221 0 16 fXX 64 44 0 12 fXX 64 26 0 16 fXX 32 13 0 16 4 800 fXX 8 221 0 16 fXX 32 44 0 12 fXX 32 26 0 16 fXX 16 13 0 16 9 600 fXX 4 221 0 16 fXX 16 44 0 12 fXX 16 26 0 16 fXX 8 13 0 16 19 200 fXX 2 221 0 16 fXX 8 44 0 12 fXX 8 26 0 16 fXX 4 13 0 16 31 250 fXX 2 136 0 00 fXX 4 54 0 00 fXX 4 32 0 00 fXX 2 16 0 00 38 400 fXX 221 0 16 fXX 4 44 0 12 fXX 4 26 0 16 fXX 2 13 0 16 76 800 fXX 111 0 29 fX...

Page 327: ...arity bit Minimum allowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 12 14 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the BRGCn register If all data up to the final data stop bit is in time for thi...

Page 328: ...x 11 BRmin 1 The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 12 4 Maximum and Minimum Allowable Baud Rate Error Division Ratio k Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 ...

Page 329: ...using UARTn are shown below 1 When the supply of clocks to UARTn is stopped for example in IDLE or STOP mode operation stops with each register retaining the value it had immediately before the supply of clocks was stopped The TXDn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped However operation is not guaranteed after the supply of clocks is...

Page 330: ...ransmit receive data can be written to or read from the SIOn register 1 Clocked serial interface mode register n CSIMn The CSIMn register is an 8 bit register for specifying the operation of CSIn 2 Clocked serial interface clock selection register n CSICn The CSICn register is an 8 bit register for controlling the transmit operation of CSIn 3 Serial I O shift register n SIOn The SIOn register is a...

Page 331: ...ther or not an interrupt request is generated when the serial clock counter has counted eight serial clocks Figure 12 17 Clocked Serial Interface Block Diagram Selector CKSn0 to CKSn2 INTCSIn CSOTn SOn Transfer clock controller Transfer mode controller Transfer data controller Transmit buffer SOTBn Selector SOn latch SIn SCKn Shift register SIOn fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 TOFm CSIEn TR...

Page 332: ... n CSIMn The CSIn register controls the operation of CSIn This register can be read or written in 8 bit or 1 bit units Caution To use CSIn be sure to set the external pins related to the CSIn function to control mode and set the CSICn register Then set the CSIEn bit to 1 before setting the other bits Remark n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 ...

Page 333: ...ssion reception mode TRMDn 0 1 Transmission mode specification If TRMDn 0 reception only transfers are performed In addition the SOn pin output is fixed at low level Data reception is started by reading the SIOn register If TRMDn 1 transmission reception is started by writing data to the SOTBn register The TRMDn bit can be overwritten only when CSOTn 0 MSB first LSB first DIRn 0 1 Transfer directi...

Page 334: ...0 After reset 00H R W Address CSIC0 FFFFFD01H CSIC1 FFFFFD11H CSIC2 FFFFFD21H CSIC3 FFFFFD31H CSIC4Note 1 FFFFFD41H CKSn2 0 0 0 0 1 1 1 1 CKSn1 0 0 1 1 0 0 1 1 CKSn0 0 1 0 1 0 1 0 1 Input clock fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 TOm outputNote 2 External clock SCKn Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode Mode D7 D6 D5 D4 D3 D2 D1 D0 SCKn I...

Page 335: ...ration 10 MHz Operation 8 MHz Operation 4 MHz Operation 0 0 0 Setting prohibited Setting prohibited 5 000 000 4 000 000 2 000 000 0 0 1 4 250 000 3 375 000 2 500 000 2 000 000 1 000 000 0 1 0 2 125 000 1 687 500 1 250 000 1 000 000 500 000 0 1 1 1 062 500 843 750 625 000 500 000 250 000 1 0 0 531 250 421 875 312 500 250 000 125 000 1 0 1 265 625 210 938 156 250 125 000 62 500 ...

Page 336: ...S SA3 only Remark n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 4 Receive only serial I O shift register n SIOEn The SIOEn register is an 8 bit shift register that converts parallel data into serial data A receive operation does not start even if the SIOEn register is read while the TRMDn bit of the CSIMn register is 0 Therefore this register is used to read the value of the SIOn register receive data w...

Page 337: ...started by writing data to the SOTBn register RESET input clears the SOTBn register to 00H This register can be read or written in 8 bit units Caution The SOTBn register can be accessed only when the system is in an idle state CSOTn bit 0 in the CSIMn register SOTBn7 SOTBn SOTBn6 SOTBn5 SOTBn4 SOTBn3 SOTBn2 SOTBn1 SOTBn0 After reset 00H R W Address SOTB0 FFFFFD04H SOTB1 FFFFFD14H SOTB2 FFFFFD24H S...

Page 338: ...SIMn register is changed from 0 to 1 serial transfer is not performed Remark n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 2 Serial clock a When internal clock is selected as the serial clock If reception or transmission is started a serial clock is output from the SCKn pin and the data of the SIn pin is taken into the SIOn register sequentially or data is output to the SOn pin sequentially from the SIO...

Page 339: ...ransmission data CSOTn bit SCKn Reg R W SOTBn SIOn SIn SOn INTCSIn interrupt ABH 56H ADH B5H 6AH D5H AAH 5AH Remark n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 b When TRMDn 1 DIRn 0 CKPn 0 and DAPn 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 AAH 55H Write 55H to SOTBn 55H transmission data CSOTn bit SCKn Reg R W SOTBn SIOn SIn SOn INTCSIn interrupt ABH 56H ADH B5H 6AH D5H AAH 5AH Remark n 0 to 3 V850ES SA2 n 0 ...

Page 340: ...D7 D6 D5 D4 D3 D2 D1 D0 b When CKPn 1 and DAPn 0 INTCSIn interrupt SIn capture SCKn SIOn Reg R W CSOTn bit D7 D6 D5 D4 D3 D2 D1 D0 c When CKPn 0 and DAPn 1 INTCSIn interrupt SIn capture SCKn SIOn Reg R W CSOTn bit D7 D6 D5 D4 D3 D2 D1 D0 d When CKPn 1 and DAPn 1 INTCSIn interrupt SIn capture SCKn SIOn Reg R W CSOTn bit D7 D6 D5 D4 D3 D2 D1 D0 Remark n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 ...

Page 341: ...marks 1 When the CKPn bit is overwritten the SCKn pin output changes 2 n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 2 SOn pin When CSIn operation is disabled CSIEn 0 the SOn pin output state is as follows TRMDn DAPn DIRn SOn Pin Output 0 Fixed to low level 0 SOn latch value low level 0 SOTBn7 value 1 1 1 SOTBn0 value Remarks 1 If any of the TRMDn DAPn and DIRn bits is overwritten the SOn pin output cha...

Page 342: ...conventional clocked serial interface or a display controller to the V850ES SA2 or V850ES SA3 n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 When connecting the V850ES SA2 or V850ES SA3 to several devices lines for handshake are required Since the first communication bit can be selected as MSB or LSB communication with various devices can be achieved Figure 12 20 System Configuration Example of CSI SCK M...

Page 343: ... 2 I 2 C bus mode multiple masters supported This mode is used for 8 bit data transfers with several devices via two lines a serial clock line SCL and a serial data bus line SDA This mode complies with the I 2 C bus format and the master device can output start condition data and stop condition data to the slave device via the serial data bus The slave device automatically detects these received d...

Page 344: ...CL N ch open drain output N ch open drain output Data hold time correction circuit Acknowledge output circuit Wake up controller Acknowledge detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Prescaler INTIIC fXX TM4 output LREL WREL SPIE WTIM ACKE STT SPT MSTS ALD EXC COI TRC ACKD STD SPD Start condition de...

Page 345: ...iguration example is shown below Figure 12 22 Example of Serial Bus Configuration Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Master CPU1 Slave CPU1 Address 1 Serial data bus Serial clock Master CPU2 Slave CPU2 Address 2 ...

Page 346: ... register can be used for both transmission and reception Write and read operations to the IIC register are used to control the actual transmit and receive operations IIC is set by an 8 bit memory manipulation instruction RESET input clears the IIC register to 00H 2 Slave address register SVA The SVA register sets local addresses when in slave mode The SVA register is set by an 8 bit memory manipu...

Page 347: ...e serial clock set by WTIM bit Note Interrupt request generated when a stop condition is detected set by SPIE bit Note Note WTIM bit Bit 3 of IIC control register IICC SPIE bit Bit 4 of IIC control register IICC 8 Serial clock controller In master mode this circuit generates the clock output via the SCL pin from a sampling clock 9 Serial clock wait controller This circuit controls the wait timing ...

Page 348: ...d IIC shift register IIC Slave address register SVA 1 IIC control register IICC The IICC register is used to enable disable I 2 C operations set wait timing and set other I 2 C operations The IICC register can be set by an 8 bit or 1 bit memory manipulation instruction RESET input clears the IICC register to 00H Caution When using the I 2 C bus mode set the port in the control mode refer to 12 1 2...

Page 349: ... sets standby mode This setting is automatically cleared after being executed Its uses include cases in which a locally irrelevant extension code has been received The SCL and SDA lines are set to high impedance The following flags are cleared STD ACKD TRC COI EXC MSTS STT SPT The standby mode following exit from communications remains in effect until the following communication entry conditions a...

Page 350: ...mode After output of eight clocks clock output is set to low level and wait is set Slave mode After input of eight clocks the clock is set to low level and wait is set for master device Interrupt request is generated at the eighth clock s falling edge Master mode After output of eight clocks clock output is set to low level and wait is set Slave mode After input of eight clocks the clock is set to...

Page 351: ... released in STOP mode Generates a start condition for starting as master The SDA line is changed from high level to low level and then the start condition is generated Next after the rated amount of time has elapsed SCL is changed to low level When bus is not used This trigger functions as a start condition reserve flag When set it releases the bus and then automatically generates a start conditi...

Page 352: ...e generated during the high level period of the ninth clock When a ninth clock must be output WTIM should be changed from 0 to 1 during the wait period following output of eight clocks and SPT should be set during the wait period that follows output of the ninth clock Stop condition is not generated Stop condition is generated termination of master device s transfer After the SDA line goes to low ...

Page 353: ... cleared after IICS is readNote When IICE changes from 1 to 0 When RESET is input Condition for setting ALD 1 When the arbitration result is a loss ALD 0 1 This status means either that there was no arbitration or that the arbitration result was a win This status indicates the arbitration result was a loss MSTS is cleared Detection of arbitration loss Condition for clearing EXC 0 When a start cond...

Page 354: ...ted When not used for communication Condition for setting TRC 1 Master When a start condition is generated Slave When 1 is input by the first byte s LSB transfer direction specification bit Condition for setting COI 1 When the received address matches the local address SVA set at the rising edge of the eighth clock Receive status other than transmit status The SDA line is set to high impedance Tra...

Page 355: ...dicates that the address transfer period is in effect Condition for clearing STD 0 When a stop condition is detected At the rising edge of the next byte s first clock following address transfer Cleared by LREL 1 When IICE changes from 1 to 0 When RESET is input Condition for setting STD 1 When a start condition is detected Stop condition was not detected Stop condition was detected The master devi...

Page 356: ...low level SCL line was detected at high level Detection of SCL line level valid only when IICE 1 IICCL 0 CLD DAD SMC DFC CL1 CL0 After reset 00H R WNote Address FFFFFD84H Condition for clearing DAD 0 When the SDA line is low level When IICE 0 When RESET is input Condition for setting DAD 1 When the SDA line is high level DAD 0 1 SDA line was detected at low level SDA line was detected at high leve...

Page 357: ...0 0 0 CLX 5 I 2 C transfer clock setting method The I 2 C transfer clock frequency fSCL is calculated using the following expression fSCL 1 m T tR tF m 12 24 48 36 54 44 86 172 132 198 see Table 12 6 Transfer Clock Setting T 1 fXX tR SCL rise time tF SCL fall time For example the I 2 C transfer clock frequency fSCL when fXX 16 MHz m 198 tR 200 ns and tF 50 ns is calculated using the following expr...

Page 358: ...1 0 fXX 24 8 00 MHz to 8 38 MHz 1 1 1 0 fXX 12 4 00 MHz to 4 19 MHz Normal mode SMC 0 1 1 1 1 Setting prohibited Remarks 1 Don t care 2 When the transfer clock is set to timer output the P96 TO4 A6 pin does not need to be set in timer output mode 6 IIC shift register IIC The IIC register is used for serial transmission reception shift operations that are synchronized with the serial clock It can b...

Page 359: ...ter and slave devices Input is Schmitt input SDA This pin is used for serial data I O This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 12 24 Pin Configuration Diagram VDD SCL SDA SCL SDA VDD Clock output Mast...

Page 360: ...r the master or slave device normally it is output by the device that receives 8 bit data The serial clock SCL is continuously output by the master device However in the slave device SCL s low level period can be extended and a wait can be inserted 1 Start condition A start condition is met when the SCL pin is at high level and the SDA pin changes from high level to low level The start conditions ...

Page 361: ...ve address register SVA If the 7 bit data matches the SVA register values the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition Figure 12 27 Address Address SCL 1 SDA INTIIC Note 2 3 4 5 6 7 8 9 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R W Note INTIIC is not generated if data other than a local address or extension code is rec...

Page 362: ...0 it indicates that the master device is transmitting data to a slave device When the transfer direction specification bit has a value of 1 it indicates that the master device is receiving data from a slave device Figure 12 28 Transfer Direction Specification SCL 1 SDA INTIIC 2 3 4 5 6 7 8 9 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R W Transfer direction specification Note Note INTIIC is not generated if data ...

Page 363: ...he 7 address data bits causes bit 3 TRC of the IIC status register IICS to be set When the TRC bit s value is 0 it indicates receive mode Therefore ACKE should be set to 1 When the slave device is receiving when TRC 0 if the slave device does not need to receive any more data after receiving several bytes setting ACKE to 0 will prevent the master device from starting transmission of the subsequent...

Page 364: ...nal that the master device outputs to the slave device when serial transfer has been completed The slave device includes hardware that detects stop conditions Figure 12 30 Stop Condition H SCL SDA A stop condition is generated when bit 0 SPT of the IIC control register IICC is set to 1 When the stop condition is detected bit 0 SPD of the IIC status register IICS is set to 1 and INTIIC is generated...

Page 365: ...us has been canceled for both the master and slave devices the next data transfer can begin Figure 12 31 Wait Signal 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait Master transmission slave reception and ACKE 1 SCL 6 SDA 7 8 9 1 2 3 SCL IIC 6 H 7 8 1 2 3 D2 D1 D0 ACK D7 D6 D5 9 IIC SCL ACKE Master Master returns to high impedance but slave is in wait state ...

Page 366: ... Output according to previously set ACKE value Transfer lines Remark ACKE Bit 2 of IIC control register IICC WREL Bit 5 of IIC control register IICC A wait may be automatically generated depending on the setting of bit 3 WTIM of the IIC control register IICC Normally when bit 5 WREL of the IICC register is set to 1 or when FFH is written to the IIC shift register IIC the wait status is canceled an...

Page 367: ...tart Address Data Data Stop normal transmission reception 1 When WTIM 0 SPT 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICS 10XXX110B 2 IICS 10XXX000B 3 IICS 10XXX000B WTIM 0 4 IICS 10XXXX00B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 SPT 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 10XXX110B 2 IICS 10XXX100B ...

Page 368: ...XX110B 2 IICS 10XXX000B WTIM 1 3 IICS 10XXXX00B WTIM 0 4 IICS 10XXX110B WTIM 0 5 IICS 10XXX000B WTIM 1 6 IICS 10XXXX00B 7 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 STT 1 SPT 1 ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICS 10XXX110B 2 IICS 10XXXX00B 3 IICS 10XXX110B 4 IICS 10XXXX00B 5 IICS 00000001B Remark Alwa...

Page 369: ...K D7 to D0 AK SP 1 2 3 4 5 1 IICS 1010X110B 2 IICS 1010X000B 3 IICS 1010X000B WTIM 1 4 IICS 1010XX00B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 SPT 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 1010X110B 2 IICS 1010X100B 3 IICS 1010XX00B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care ...

Page 370: ... WTIM 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 0001X110B 2 IICS 0001X000B 3 IICS 0001X000B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 0001X110B 2 IICS 0001X100B 3 IICS 0001XX00B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care ...

Page 371: ...K SP 1 2 3 4 5 1 IICS 0001X110B 2 IICS 0001X000B 3 IICS 0001X110B 4 IICS 0001X000B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 after restart matches with SVA ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICS 0001X110B 2 IICS 0001XX00B 3 IICS 0001X110B 4 IICS 0001XX00B 5 IICS 00000001B Remark Always generated Gener...

Page 372: ...4 5 1 IICS 0001X110B 2 IICS 0001X000B 3 IICS 0010X010B 4 IICS 0010X000B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICS 0001X110B 2 IICS 0001XX00B 3 IICS 0010X010B 4 IICS 0010X110B 5 IICS 0010XX00B 6 IICS 00000001B Remark Always...

Page 373: ...D0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICS 0001X110B 2 IICS 0001X000B 3 IICS 00000X10B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 after restart does not match with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 1 IICS 0001X110B 2 IICS 0001XX00B 3 IICS 00000X10B 4 IICS 00000001B Remark Always gene...

Page 374: ... RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 0010X010B 2 IICS 0010X000B 3 IICS 0010X000B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICS 0010X010B 2 IICS 0010X110B 3 IICS 0010X100B 4 IICS 0010XX00B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care ...

Page 375: ...4 5 1 IICS 0010X010B 2 IICS 0010X000B 3 IICS 0001X110B 4 IICS 0001X000B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 after restart matches with SVA ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 1 IICS 0010X010B 2 IICS 0010X110B 3 IICS 0010XX00B 4 IICS 0001X110B 5 IICS 0001XX00B 6 IICS 00000001B Remark Always generat...

Page 376: ...0010X010B 2 IICS 0010X000B 3 IICS 0010X010B 4 IICS 0010X000B 5 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 after restart extension code reception ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 6 7 1 IICS 0010X010B 2 IICS 0010X110B 3 IICS 0010XX00B 4 IICS 0010X010B 5 IICS 0010X110B 6 IICS 0010XX00B 7 IICS 00000001B Remar...

Page 377: ... to D0 AK SP 1 2 3 4 1 IICS 0010X010B 2 IICS 0010X000B 3 IICS 00000X10B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 after restart does not match with address not extension code ST AD6 to AD0 RW AK D7 to D0 AK ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 4 5 1 IICS 0010X010B 2 IICS 0010X110B 3 IICS 0010XX00B 4 IICS 00000X10B 5 IICS 00000001B Remark Alw...

Page 378: ...during transmission of slave address data 1 When WTIM 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 0101X110B Example When ALD is read during interrupt servicing 2 IICS 0001X000B 3 IICS 0001X000B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 0101X110B Example When ALD is...

Page 379: ...Example When ALD is read during interrupt servicing 2 IICS 0010X000B 3 IICS 0010X000B 4 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care 2 When WTIM 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICS 0110X010B Example When ALD is read during interrupt servicing 2 IICS 0010X110B 3 IICS 0010X100B 4 IICS 0010XX00B 5 IICS 00000001B Remark Always generated G...

Page 380: ...AK D7 to D0 AK SP 1 2 1 IICS 01000110B Example When ALD is read during interrupt servicing 2 IICS 00000001B Remark Always generated Generated only when SPIE 1 b When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 1 IICSn 0110X010B Example When ALD is read during interrupt servicing IICC s LREL is set to 1 via software 2 IICS 0000000...

Page 381: ...0 AK SP 1 2 3 1 IICS 10001110B 2 IICS 01000000B Example When ALD is read during interrupt servicing 3 IICS 00000001B Remark Always generated Generated only when SPIE 1 2 When WTIM 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 1 IICS 10001110B 2 IICS 01000100B Example When ALD is read during interrupt servicing 3 IICS 00000001B Remark Always generated Generated only when SPIE 1 ...

Page 382: ...1000X110B 2 IICS 01000110B Example When ALD is read during interrupt servicing 3 IICS 00000001B Remark Always generated Generated only when SPIE 1 X Don t care Dn D6 to D0 2 Extension code ST AD6 to AD0 RW AK D7 to Dn ST AD6 to AD0 RW AK D7 to D0 AK SP 1 2 3 1 IICS 1000X110B 2 IICS 0110X010B Example When ALD is read during interrupt servicing IICC s LREL is set to 1 via software 3 IICS 00000001B R...

Page 383: ...enerated Generated only when SPIE 1 X Don t care Dn D6 to D0 f When arbitration loss occurs due to low level data when attempting to generate a restart condition When WTIM 1 STT 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 1000X110B 2 IICS 1000XX00B 3 IICS 01000100B Example When ALD is read during interrupt servicing 4 IICS 00000001B Remark Always generated Generated...

Page 384: ... IICS 1000XX00B 3 IICS 01000001B Remark Always generated Generated only when SPIE 1 X Don t care h When arbitration loss occurs due to low level data when attempting to generate a stop condition When WTIM 1 SPT 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICS 1000X110B 2 IICS 1000XX00B 3 IICS 01000000B Example When ALD is read during interrupt servicing 4 IICS 00000001B ...

Page 385: ...either the INTIIC signal nor a wait occurs Remark The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 1 During address transmission reception Slave device operation The interrupt and wait timing are determined regardless of the WTIM bit Master device operation The int...

Page 386: ...00 or 1111 the extension code flag EXC is set for extension code reception and an interrupt request INTIIC is issued at the falling edge of the eighth clock The local address stored in the slave address register SVA is not affected 2 If 11110xx0 is set to SVA by a 10 bit address transfer and 11110xx0 is transferred from the master device the results are as follows Note that the INTIIC signal occur...

Page 387: ...IIC status register IICS is set via the timing by which the arbitration loss occurred and the SCL and SDA lines are both set to high impedance which releases the bus The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a stop condition is detected etc and the ALD 1 setting that has been made by software For details of interrupt request t...

Page 388: ...e 2 When data is at low level while attempting to output a restart condition At falling edge of eighth or ninth clock following byte transferNote 1 When stop condition is detected while attempting to output a restart condition When stop condition is output when SPIE 1 Note 2 When data is at low level while attempting to output a stop condition When SCL is at low level while attempting to output a ...

Page 389: ... interrupt requests from occurring when addresses do not match When a start condition is detected wakeup standby mode is set This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device which has output a start condition to a slave device However when a stop condition is detected bit 5 SPIE of the IIC control reg...

Page 390: ...us release is detected when a stop condition is detected writing to the IIC shift register IIC causes the master s address transfer to start At this point bit 4 SPIE of IICC should be set When the STT bit has been set the operation mode as start condition or as communication reservation is determined according to the bus status If the bus has been released a start condition is generated If the bus...

Page 391: ... STD Output by master with bus access IIC IIC shift register STT Bit 1 of IIC control register IICC STD Bit 1 of IIC status register IICS SPD Bit 0 of IIC status register IICS Communication reservations are accepted of the following timing After bit 1 STD of the IIC status register IICS is set to 1 a communication reservation can be made by setting bit 1 STT of the IIC control register IICC to 1 b...

Page 392: ...es IIC H EI MSTS 0 Communication reservation Note Generate start condition Sets STT flag communication reservation Secures wait period set by software see Table 12 10 Confirmation of communication reservation Clear user flag IIC write operation Defines that communication reservation is in effect defines and sets user flag to any part of RAM Note The communication reservation operation executes a w...

Page 393: ...ation mode first generate a stop condition to release the bus then perform master device communication When using multiple masters it is not possible to perform master device communication when the bus has not been released when a stop condition has not been detected Use the following sequence for generating a stop condition 1 Set the IIC clock selection register IICCL 2 Set bit 7 IICE of the IIC ...

Page 394: ... SPIE WTIM 1 SPT 1 Start IIC write transfer Start IIC write transfer WREL 1 Start reception Generate stop condition no slave with matching address Generate restart condition or stop condition START Data processing Data processing ACKE 0 No Yes No No No No No No Yes Yes Yes Yes Yes INTIIC 1 WTIM 0 ACKE 1 INTIIC 1 Transfer completed INTIIC 1 ACKD 1 TRC 1 INTIIC 1 ACKD 1 Stop condition detection Init...

Page 395: ... 37 Slave Operation Flow Chart IICC H IICE 1 WREL 1 Start reception Detect restart condition or stop condition START ACKE 0 Data processing Data processing LREL 1 No Yes No No No No No No No Yes No Yes Yes Yes Yes Yes Yes WTIM 0 ACKE 1 INTIIC 1 Yes Communicate Transfer completed INTIIC 1 WTIM 1 Start IIC write transfer INTIIC 1 EXC 1 COI 1 TRC 1 ACKD 1 ...

Page 396: ... the master device transmits the TRC bit bit 3 of the IIC status register IICS which specifies the data transfer direction and then starts serial communication with the slave device The shift operation of the IIC bus shift register IIC is synchronized with the falling edge of the serial clock SCL The transmit data is transferred to the SO latch and is output MSB first via the SDA pin Data input vi...

Page 397: ... IIC ACKD STD SPD WTIM H H L L L L H H H L L ACKE MSTS STT SPT WREL INTIIC TRC IIC ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 IIC address IIC data IIC FFH Transmit Start condition Receive When EXC 1 Note Note Note To cancel slave wait write ...

Page 398: ...CKD STD SPD WTIM H H L L L L L L H H H H L L L L L ACKE MSTS STT SPT WREL INTIIC TRC IIC ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IIC data IIC FFH Note IIC FFH Note IIC data Transmit Receive Note Note Note To cancel slave wait write FFH to IIC or ...

Page 399: ...WTIM H H L L L L H H H L ACKE MSTS STT SPT WREL INTIIC TRC IIC ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IIC data IIC address IIC FFH Note IIC FFH Note Stop condition Start condition Transmit Note Note When SPIE 1 Receive When SPIE 1 Note To cancel slave wai...

Page 400: ...ition address IIC ACKD STD SPD WTIM H H L L H H L ACKE MSTS STT L L SPT WREL INTIIC TRC IIC ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2 D5 D6 D7 IIC address IIC FFH Note Note IIC data Start condition Note To cancel slave wait write FFH to IIC or...

Page 401: ...STD SPD WTIM H H H L L L L L L H H H L L L L L ACKE MSTS STT SPT WREL INTIIC TRC IIC ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IIC data IIC data IIC FFH Note IIC FFH Note Note To cancel slave wait write FFH to IIC...

Page 402: ... IIC ACKD STD SPD WTIM H H L L L H H ACKE MSTS STT SPT WREL INTIIC TRC IIC ACKD STD SPD WTIM ACKE MSTS STT SPT WREL INTIIC TRC SCL SDA Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IIC address IIC FFH Note Note IIC data Stop condition Start condition When SPIE 1 N ACK When SPIE 1 Note To cancel slave wait write FFH to II...

Page 403: ...rupts from external input pins or software triggers memory refers to internal RAM or external memory 13 1 Features 4 independent DMA channels Transfer unit 8 16 bits Maximum transfer count 65 536 2 16 Transfer type Two cycle transfer Transfer mode Single transfer mode Transfer requests Request by interrupts from on chip peripheral I O serial interface timer counter A D converter or interrupts from...

Page 404: ...ol Address control Count control Channel control DMAC V850ES SA2 V850ES SA3 Bus interface External bus External RAM External ROM External I O DMA source address register n DSAnH DSAnL DMA transfer count register n DBCn DMA channel control register n DCHCn DMA destination address register n DDAnH DDAnL DMA addressing control register n DADCn DMA trigger factor register n DTFRn Remark n 0 to 3 ...

Page 405: ...ce addresses A25 to A16 During DMA transfer they store the next DMA transfer source address SA25 to SA16 After reset Undefined R W Address DSA0H FFFFF082H DSA1H FFFFF08AH DSA2H FFFFF092H DSA3H FFFFF09AH SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 IR 0 0 0 0 0 SA25 SA24 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 2 DMA source address registers 0L to 3L DSA0L to DSA3L These registers can be read or written in...

Page 406: ...ss DDA0H FFFFF086H DDA1H FFFFF08EH DDA2H FFFFF096H DDA3H FFFFF09EH DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 IR 0 0 0 0 0 DA25 DA24 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 Set the DMA destination addresses A25 to A16 During DMA transfer they store the next DMA transfer destination address DA25 to DA16 2 DMA destination address registers 0L to 3L DDA0L to DDA3L These registers can be read or written in...

Page 407: ...register being overwritten the value set immediately before the DMA transfer will be read out 0000H will not be read even if DMA transfer has ended DBCn n 0 to 3 Byte transfer count 1 or remaining byte transfer count Byte transfer count 2 or remaining byte transfer count Byte transfer count 65 536 216 or remaining byte transfer count BC15 to BC0 0000H 0001H FFFFH Byte transfer count setting or rem...

Page 408: ...DCn n 0 to 3 8 bits 16 bits DS0 0 1 Setting of transfer data size for DMA transfer Increment Decrement Fixed Setting prohibited SAD1 0 0 1 1 SAD0 0 1 0 1 Setting of count direction of the source address for DMA channel n Increment Decrement Fixed Setting prohibited DAD1 0 0 1 1 DAD0 0 1 0 1 Setting of count direction of the destination address for DMA channel n After reset 0000H R W Address DADC0 ...

Page 409: ...es whether DMA transfer through DMA channel n has ended or not DMA transfer disabled DMA transfer enabled This bit is cleared to 0 when DMA transfer ends It is also cleared to 0 when DMA transfer is forcibly terminated by means of NMI input Enn 0 1 Setting of whether DMA transfer through DMA channel n is to be enabled or disabled If this bit is set to 1 in the DMA transfer enable state TCn bit 0 E...

Page 410: ... request DFnNote 0 1 Setting of interrupt source that serves as the DMA start factor After reset 00H R W Address DTFR0 FFFFF810H DTFR1 FFFFF812H DTFR2 FFFFF814H DTFR3 FFFFF816H DFn 0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 0 1 2 3 4 5 6 7 Note The DFn bit is a write only bit Write 0 to this bit to clear a DMA transfer request if the interrupt that is specified as the cause of starting DMA transfer whi...

Page 411: ...0 1 0 0 1 INTRTC 0 0 1 0 1 0 INTCC00 0 0 1 0 1 1 INTCC01 0 0 1 1 0 0 INTOVF0 0 0 1 1 0 1 INTCC10 0 0 1 1 1 0 INTCC11 0 0 1 1 1 1 INTOVF1 0 1 0 0 0 0 INTTM2 0 1 0 0 0 1 INTTM3 0 1 0 0 1 0 INTTM4 0 1 0 0 1 1 INTTM5 0 1 0 1 0 0 INTCSI0 0 1 0 1 0 1 INTIIC 0 1 0 1 1 0 INTCSI1 0 1 0 1 1 1 INTSRE0 0 1 1 0 0 0 INTSR0 0 1 1 0 0 1 INTST0 0 1 1 0 1 0 INTCSI2 0 1 1 0 1 1 INTSRE1 0 1 1 1 0 0 INTSR1 0 1 1 1 0 1...

Page 412: ...e In the last T2R state read data is sampled After entering the last T2R state the bus invariably enters the T1W state 6 T2RI state State in which the bus is ready for DMA transfer to on chip peripheral I O or internal RAM state in which the bus mastership is acquired for DMA transfer to on chip peripheral I O or internal RAM After entering the last T2RI state the bus invariably enters the T1W sta...

Page 413: ...V0UD 413 13 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 13 1 DMAC Bus Cycle Two Cycle Transfer State Transition TI T0 T1R T1RI T2R T1W T2W TE TI T2RI T1WI ...

Page 414: ...ccurs When the DMAC has released the bus if another higher priority DMA transfer request is issued the higher priority DMA request always takes precedence 13 6 Transfer Types 13 6 1 Two cycle transfer In two cycle transfer data transfer is performed in two cycles a read cycle source to DMAC and a write cycle DMAC to destination In the first cycle the source address is output and reading is perform...

Page 415: ...e data bus width of the transfer source and that of the transfer destination are different the operation becomes as follows In the case of transfer from a 16 bit bus to an 8 bit bus A 16 bit read cycle is generated and then an 8 bit write cycle is generated twice In the case of transfer from an 8 bit bus to a 16 bit bus An 8 bit read cycle is generated twice and then a 16 bit write cycle is genera...

Page 416: ... factors as shown below 1 Request from software If the STGn Enn and TCn bits of the DCHCn register are set as follows DMA transfer starts n 0 to 3 STGn bit 1 Enn bit 1 TCn bit 0 2 Request from on chip peripheral I O If when the Enn and TCn bits of the DCHCn register are set as shown below an interrupt request is issued from the on chip peripheral I O that is set in the DTFRn register DMA transfer ...

Page 417: ...ution clock for DMA transfer are shown below Internal RAM access 2 clocks Note that for external memory access the time depends on the type of external memory connected 4 Bus arbitration for CPU The CPU can access external memory on chip peripheral I O and internal RAM not undergoing DMA transfer While data transfer among external memories or to and from I O is being performed the CPU can access i...

Page 418: ...ion software exception or by generation of an exception event i e fetching of an illegal opcode exception trap 14 1 Features Interrupts Non maskable interrupts 2 sources Maskable interrupts µPD703201 70F3201 External 7 Internal 29 sources µPD703201Y 70F3201Y External 7 Internal 30 sources µPD703204 70F3204 External 7 Internal 30 sources µPD703204Y 70F3204Y External 7 Internal 31 sources 8 levels o...

Page 419: ... INTP6 INTP6 pin valid edge input Pin 00F0H 000000F0H nextPC PIC6 8 INTRTC RTC interrupt RTC 0100H 00000100H nextPC RTCIC 9 INTCC00 CC00 capture trigger input TM0 CC00 match TM0 0110H 00000110H nextPC CCIC00 10 INTCC01 CC01 capture trigger input TM0 CC01 match TM0 0120H 00000120H nextPC CCIC01 11 INTOVF0 TM0 overflow TM0 0130H 00000130H nextPC OVFIC0 12 INTCC10 CC10 capture trigger input TM1 CC10 ...

Page 420: ...B0H nextPC DMAIC3 36 INTROV RTC overflow RTC 02C0H 000002C0H nextPC ROVIC Maskable Interrupt 37 INTBRG BRG match BRG 02D0H 000002D0H nextPC BRGIC Notes 1 µPD703201Y 70F3201Y 703204Y 70F3204Y only 2 V850ES SA3 only Remarks 1 Default Priority The priority order when two or more maskable interrupt requests occur at the same time The highest priority is 0 Restored PC The value of the program counter P...

Page 421: ...hile NMI is being serviced The new NMI request is held pending regardless of the value of the NP bit of the program status word PSW in the CPU The pending NMI interrupt is acknowledged after the NMI currently under execution has been serviced after the RETI instruction has been executed 2 If INTWDT request is issued while NMI is being serviced The INTWDT request is held pending if the NP bit of th...

Page 422: ...Held pending Servicing of pending NMI NMI request Main routine System reset NMI request NMI servicing Held pending INTWDT servicing INTWDT request INTWDT request generated during NMI servicing NP 0 set before INTWDT request Main routine System reset NMI request NMI servicing INTWDT servicing INTWDT request NP 0 INTWDT request generated during NMI servicing NP 0 set after INTWDT request Main routin...

Page 423: ...word FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H 00000020H corresponding to the non maskable interrupt to the PC and transfers control The servicing configuration of a non maskable interrupt is shown in Figure 14 2 Figure 14 2 Servicing Configuration of Non Maskable Interrupt PSW NP FEPC FEPSW ECR FECC PSW NP PSW EP PSW ID PC Restored...

Page 424: ...14 3 illustrates how the RETI instruction is processed Figure 14 3 RETI Instruction Processing PSW EP RETI instruction PSW NP Original processing restored 1 1 0 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt servicing in order to restore the PC and PSW correctly during recovery by the RETI instructi...

Page 425: ...t cannot be detected as an edge i e the edge is detected after specific time The NMI pin is used to release the software STOP mode Because the internal system clock is stopped in the software STOP mode noise is not eliminated by using the system clock 14 2 5 Function to detect edge of NMI pin The valid edge of the NMI pin can be selected from four types rising edge falling edge both edges and no e...

Page 426: ...ss FFFFFC20H Remark For how to specify a valid edge refer to Table 14 2 2 External interrupt falling edge specification register 0 INTF0 This is an 8 bit register that specifies detection of the falling edge of the NMI pin This register can be read or written in 8 bit or 1 bit units Caution When the function is changed from the external interrupt function alternate function to the port function an...

Page 427: ...To enable multiple interrupts however save EIPC and EIPSW to memory or registers before executing the EI instruction and execute the DI instruction before the RETI instruction to restore the original values of EIPC and EIPSW If the WDTM4 bit of the watchdog timer mode register WDTM is cleared to 0 the watchdog timer overflow interrupt functions as a maskable interrupt INTWDTM 14 3 1 Operation If a...

Page 428: ... of other interrupt request Highest default priority of interrupt requests with the same priority EIPC EIPSW ECR EICC PSW EP PSW ID Corresponding bit of ISPRNote PC Restored PC PSW Exception code 0 1 1 Handler address Note For the ISPR register see 14 3 6 In service priority register ISPR The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is bei...

Page 429: ... PSW Figure 14 5 illustrates the processing of the RETI instruction Figure 14 5 RETI Instruction Processing PSW EP RETI instruction PSW NP Restores original processing 1 1 0 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 PC PSW FEPC FEPSW Note For the ISPR register see 14 3 6 In service priority register ISPR Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction d...

Page 430: ...iority level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 14 1 Interrupt Exception Source List The programmable priority control customizes interrupt requests into eight levels by setting the priority level spec...

Page 431: ...d is higher than that of c d is held pending because interrupts are disabled Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request b level 2 Interrupt request d level 2 Interrupt request f level 3 Caution To per...

Page 432: ... request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status Pending interrupt requests are acknowledged after servicing of interrupt request l At this time interrupt request n is acknowledged first even...

Page 433: ...acknowledged first according to their priorities Because the priorities of b and c are the same b is acknowledged first according to the default priority Caution To perform multiple interrupt servicing the values of the EIPC and EIPSW registers must be saved before executing the EI instruction When returning from multiple interrupt servicing restore the values of EIPC and EIPSW after executing the...

Page 434: ...enabled Interrupt servicing disabled pending xxMKn 0 1 Interrupt mask flag Specifies level 0 highest Specifies level 1 Specifies level 2 Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 lowest xxPRn2 0 0 0 0 1 1 1 1 Interrupt priority specification bit xxPRn1 0 0 1 1 0 0 1 1 xxPRn0 0 1 0 1 0 1 0 1 After reset 47H R W Address FFFFF110H to FFFFF15AH 6 7 Note ...

Page 435: ...F132H TMIC4 TMF4 TMMK4 0 0 0 TMPR42 TMPR41 TMPR40 FFFFF134H TMIC5 TMF5 TMMK5 0 0 0 TMPR52 TMPR51 TMPR50 FFFFF136H CSIIC0 CSIIF0 CSIMK0 0 0 0 CSIPR02 CSIPR01 CSIPR00 FFFFF138H IICICNote 1 IICIF IICMK 0 0 0 IICPR2 IICPR1 IICPR0 FFFFF13AH CSIIC1 CSIIF1 CSIMK1 0 0 0 CSIPR12 CSIPR11 CSIPR10 FFFFF13CH SREIC0 SREIF0 SREMK0 0 0 0 SREPR02 SREPR01 SREPR00 FFFFF13EH SRIC0 SRIF0 SRMK0 0 0 0 SRPR02 SRPR01 SRPR...

Page 436: ...d If a bit is manipulated using the name of xxMKn the contents of the xxICn register instead of the IMRm register are rewritten as a result the contents of the IMRm register are also rewritten TMMK2 PMK6 IMR0 OVFMK1 PMK5 CCMK11 PMK4 CCMK10 PMK3 OVFMK0 PMK2 CCMK01 PMK1 CCMK00 PMK0 RTCMK WDTMK After reset FFFFH R W Address FFFFF100H After reset FFFFH R W Address FFFFF102H After reset FFFFH R W Addre...

Page 437: ... ISPR1 ISPR0 After reset 00H R Address FFFFF1FAH 7 6 5 4 3 2 1 0 Remark n 0 to 7 priority level 14 3 7 Maskable interrupt status flag This flag controls the maskable interrupt s operating state and stores control information regarding enabling or disabling of interrupt requests An interrupt disable flag ID is incorporated which is assigned to the PSW 0 NP EP ID SAT CY OV S Z PSW Maskable interrupt...

Page 438: ...2H Interval timer mode Maskable interrupt INTWDTM occurs if overflow occurs Watchdog timer mode 1 Non maskable interrupt INTWDT occurs if overflow occurs Watchdog timer mode 2 Reset operation WDTRES is started if overflow occurs WDTM4 0 0 1 1 WDTM3 0 1 0 1 Watchdog timer operation mode selectionNote 2 7 14 3 9 Eliminating noise on INTP0 to INTP6 pins The INTP0 to INTP6 pins have a noise eliminator...

Page 439: ...how to specify a valid edge refer to Table 14 4 2 External interrupt falling edge specification register 0 INTF0 This is an 8 bit register that specifies detection of the falling edge of the INTP0 to INTP4 pins This register can be read or written in 8 bit or 1 bit units Caution When the function is changed from the external interrupt function alternate function to the port function an edge may be...

Page 440: ...r how to specify a valid edge refer to Table 14 5 4 External interrupt falling edge specification register 9 INTF9 This is an 8 bit register that specifies detection of the falling edge of the INTP5 and INTP6 pins This register can be read or written in 16 bit units When the lower 8 bits of the INTF9 register are used as INTF9L register however it can be read or written in 8 bit or 1 bit units Cau...

Page 441: ... ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 14 8 illustrates the processing of a software exception Figure 14 8 Software Exception Processing TRAP instruction EIPC EIPSW ECR EICC PSW EP PSW ID PC Restored PC PSW Exception code 1 1 Handler address CPU proce...

Page 442: ...ntrol to the address of the restored PC and PSW Figure 14 9 illustrates the processing of the RETI instruction Figure 14 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception processing in order to restore t...

Page 443: ...tatus flag EP The EP flag is bit 6 of the PSW and is a status flag used to indicate that exception processing is in progress It is set when an exception occurs 0 NP EP ID SAT CY OV S Z PSW Exception processing not in progress Exception processing in progress EP 0 1 Exception processing status After reset 00000020H ...

Page 444: ...ap is generated when an instruction applicable to this illegal instruction is executed 15 16 23 22 X X X X X X 0 X X X X X X X X X X 1 1 1 1 1 1 X X X X X 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to Arbitrary Caution Since it is possible to assign this instruction to an illegal opcode in the future it is recommended that it not be used 1 Operation If an exception trap occurs the CPU performs the follo...

Page 445: ... exception trap is carried out by the DBRET instruction By executing the DBRET instruction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 14 11 illustrates the restore processing from an exception trap Figure 14 11 Restore Proc...

Page 446: ...essed Figure 14 12 Pipeline Operation at Interrupt Request Acknowledgement Outline Internal clock Instruction 1 Instruction 2 Interrupt acknowledgement operation Instruction start instruction of interrupt servicing routine Interrupt request IF ID EX DF WB IFX IDX 4 system clocks IF IF ID EX INT1 INT2 INT3 INT4 Remark INT1 to INT4 Interrupt acknowledgement processing IFX Invalid instruction fetch I...

Page 447: ...een an interrupt request non sample instruction and the next instruction interrupt is held pending The interrupt request non sample instructions are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the command register PRCMD The load store or bit manipulation instructions for the following interrupt related registers Interrupt control register xx...

Page 448: ...Mode to stop only the operating clock of the CPU IDLE mode Mode to stop all the internal operations of the chip except the oscillator Software STOP mode Mode to stop all the internal operations of the chip except the subclock oscillator Subclock operation mode Mode to use the subclock as the internal system clock Sub IDLE mode Mode to stop all the internal operations of the chip except the oscilla...

Page 449: ...4 Interrupt requestNote 2 Setting of IDLE mode Interrupt requestNote 3 RESET input RESET input Notes 1 Non maskable interrupt request NMI pin input unmasked external interrupt request INTP0 to INTP6 pin input or unmasked internal interrupt request from peripheral functions operable in IDLE mode 2 Non maskable interrupt request unmasked maskable interrupt request or reset input by WDT overflow 3 No...

Page 450: ...normal operation Setting of subclock operation Setting of IDLE mode Setting of backup modeNote 2 Interrupt requestNote 1 RESET pin input RESET pin inputNote 3 Notes 1 Non maskable interrupt request NMI pin input unmasked external interrupt request INTP0 to INTP6 pin input or unmasked internal interrupt request from peripheral functions operable in sub IDLE mode 2 Turn off power other than backup p...

Page 451: ...has been released the normal operation mode is restored 1 Releasing HALT mode by non maskable interrupt request or unmasked maskable interrupt request The HALT mode is released by a non maskable interrupt request or an unmasked maskable interrupt request regardless of the priority of the interrupt request If the HALT mode is set in an interrupt servicing routine however an interrupt request that i...

Page 452: ...eration 16 bit timer event counters TM0 TM1 Operable 8 bit timer event counters TM2 to TM5 Operable Real timer counter Operable when divided fX BRG output is selected as count clock Operable Watchdog timer Operable CSI0 to CSI4 Operable I2 CNote Operable Serial interface UART0 UART1 Operable A D converter Operable D A converter Operable External bus interface Refer to CHAPTER 5 BUS CONTROL FUNCTIO...

Page 453: ...DLE mode is released by a non maskable interrupt request NMI pin input unmasked external interrupt request INTP0 to INTP6 pin input unmasked internal interrupt request from the peripheral functions operable in the IDLE mode or RESET input After the IDLE mode has been released the normal operation mode is restored 1 Releasing IDLE mode by non maskable interrupt request or unmasked maskable interrup...

Page 454: ... bit timer event counters TM2 to TM5 Stops operation Real time counter Operable when divided fX BRG output is selected as count clock Operable Watchdog timer Stops operation CSI0 to CSI4 Operable when SCKn input clock is selected as operation clock n 0 to 4 I2 CNote Stops operation Serial interface UART0 UART1 Stops operation A D converter Operable when fBRG is selected as operation clock D A conv...

Page 455: ...upt request INTP0 to INTP6 pin input unmasked internal interrupt request from the peripheral functions operable in the software STOP mode or RESET pin input After the software STOP mode has been released the normal operation mode is restored after the oscillation stabilization time has been secured 1 Releasing software STOP mode by non maskable interrupt request or unmasked maskable interrupt requ...

Page 456: ...TM1 Stops operation 8 bit timer event counters TM2 to TM5 Stops operation Real time counter Stops operation Operable when fXT is selected as count clock Watchdog timer Stops operation CSI0 to CSI4 Operable when SCKn input clock is selected as operation clock n 0 to 4 I2 CNote Stops operation Serial interface UART1 UART1 Stops operation A D converter Stops operation D A converter Stops operation Ex...

Page 457: ...counting the oscillation stabilization time is shared with watchdog timer so the oscillation stabilization time equal to the overflow time of the watchdog timer elapses Figure 15 3 shows the operation performed when the software STOP mode is released by an interrupt request Figure 15 3 Oscillation Stabilization Time Oscillated waveform Main clock oscillator stops Oscillation stabilization time cou...

Page 458: ...tion the current consumption can be further reduced to the level of the software STOP mode by stopping the operation of the main system clock oscillator Table 15 8 shows the operation status in subclock operation mode Caution When manipulating the CK3 bit do not change the set values of the CK2 to CK0 bits of the PCC register using a bit manipulation instruction to manipulate the bit is recommende...

Page 459: ...nt counters TM0 TM1 Stops operation 8 bit timer event counters TM2 to TM5 Stops operation Real time counter Operable Operable when fXT is selected as count clock Watchdog timer Stops operation CSI0 to CSI4 Operable Operable when SCKn input clock is selected as operation clock n 0 to 4 I2 CNote Operable Stops operation Serial interface UART0 UART1 Operable Stops operation A D converter Operable Sto...

Page 460: ...nput unmasked internal interrupt request from the peripheral functions operable in the sub IDLE mode or RESET pin input When the sub IDLE mode is released by an interrupt request the subclock operation mode is set If it is released by RESET pin input the normal operation mode is restored 1 Releasing sub IDLE mode by non maskable interrupt request or unmasked maskable interrupt request The sub IDLE...

Page 461: ...ration 8 bit timer event counters TM2 to TM5 Stops operation Real timer counter Operable Operable when fXT is selected as count clock Watchdog timer Stops operation CSI0 to CSI4 Operable when SCKn input clock is selected as operation clock n 0 to 4 I2 CNote Stops operation Serial interface UART0 UART1 Stops operation A D converter Stops operation D A converter Stops operation External bus interfac...

Page 462: ...bclock oscillator real time counter and internal RAM as shown in Figure 15 4 All the other internal functions including the CPU cannot operate because the power supply is stopped Figure 15 4 Backup Mode Power supply for backup Power supply for operation Connected to VSS in backup mode Backup power status flag BPSF RAM Real time counter Subclock oscillator Main clock oscillator Peripheral function ...

Page 463: ...VDDBU stop the subclock oscillator Eve if the voltage on VDDBU drops below the operable range the contents of the internal RAM can be retained if the data retention voltage is maintained A voltage drop on VDDBU can be detected i e whether the data of the internal RAM is valid or not by a backup power status register BPS refer to 15 9 2 The BPSF bit of the BPS register is set if a change of potenti...

Page 464: ...wer pin other than VDDBU Therefore it can be checked if the data of the internal RAM is valid or not by clearing the BPSF bit before the backup mode is set and checking the status of the BPSF bit by the reset processing routine after the backup mode has been released If BPSF 0 the data of the internal RAM is valid if BPSF 1 the data of the internal RAM is invalid The backup mode can be released us...

Page 465: ...mer event counters TM2 to TM5 Power supply stopped Real timer counter Operable when fXT is selected as count clock Watchdog timer Power supply stopped CSI0 to CSI4 Power supply stopped I2 CNote Power supply stopped Serial interface UART0 UART1 Power supply stopped A D converter Power supply stopped D A converter Power supply stopped External bus interface Power supply stopped Port function Power s...

Page 466: ...s software STOP mode After reset 00H R W Address FFFFF1FEH 2 Backup power status register BPS The BPS register is a special register refer to 3 4 8 Special registers It can be written only in a special sequence so that its contents are not rewritten by mistake due to a program hang up This register can be read or written in 8 bit or 1 bit units 0 BPC 0 0 0 0 0 0 BPSF After reset 01H R W Address FF...

Page 467: ...eased and the CPU starts executing the program Initialize the contents of each register in the program as necessary The RESET pin has a noise eliminator that operates by analog delay to prevent malfunction caused by noise 16 2 Configuration Figure 16 1 Reset Block Diagram RESET Count clock Analog delay circuit Reset controller Watchdog timer WDTRES issued due to overflow Reset signal to CPU Reset ...

Page 468: ...ed If the RESET pin goes high or if WDTRES is received the reset status is released If the reset status is released by RESET pin input the oscillation stabilization time elapses reset value of OSTS register 2 19 fX and then the CPU starts program execution If the reset status is released by WDTRES the oscillation stabilization time is not inserted because the main system clock oscillator does not ...

Page 469: ...ation on the subclock when the RESET signal is input If a clock resulting from dividing the main clock fX by the baud rate generator fBRG is used as the count clock the count clock is changed to fXT Table 16 2 Hardware Status on Occurrence of WDTRES Item During Reset After Reset Main clock oscillator fX Oscillation continuesNote 1 Subclock oscillator fXT Oscillation can continue without effect fro...

Page 470: ... oscillation stabilization Internal system reset signal Analog delay eliminated as noise Analog delay Analog delay eliminated as noise RESET fX fCLK Analog delay Figure 16 3 Operation on Power Application Oscillation stabilization time count Must be 2 s or longer Initialized to fXX 8 operation Overflow of timer for oscillation stabilization Internal system reset signal RESET fX VDD fCLK Analog del...

Page 471: ...external RAM or the internal RAM By using this function instruction bugs found in the mask ROM can be corrected at up to four places Figure 17 1 Block Diagram of ROM Correction Instruction address bus Block replaced by DBTRAP instruction Instruction data bus ROM DBTRAP instruction generation block Correction address register n CORADn Correction control register CORENn bit Comparator Remark n 0 to ...

Page 472: ...ection address registers CORADn are provided n 0 to 3 The CORADn register can only be read or written in 32 bit units If the higher 16 bits of the CORADn register are used as the CORADnH register and the lower 16 bits as the CORADnL register these registers can be read or written in 16 bit units Set correction addresses within the range of 0000000H to 003FFFEH Fix bits 0 and 18 to 31 to 0 Correcti...

Page 473: ...aced by the DBTRAP instruction 2 When the DBTRAP instruction is executed execution branches to address 00000060H 3 Software processing after branching causes the result of ROM correction to be judged the fetch address and ROM correction operation are confirmed and execution to branch to the correction software 4 After the correction software has been executed the return address is set and return p...

Page 474: ...Change fetch code to DBTRAP instruction Jump to ROM correction judgment address Jump to address of replacement program Execute fetch code Jump to address 60H Execute correction code Error processing Execute DBRET instruction Write return address to DBPC Write value of PSW to DBPSW as necessary Set CORCN register Yes Yes Yes Yes No No No No Processing by user program ROM correction judgment Read da...

Page 475: ... 4 bytes can be accessed by a single clock the same as in the mask ROM version Writing to flash memory can be performed with the memory mounted on the target system on board A dedicated flash programmer is connected to the target system to perform writing The following can be considered as the development environment and the applications using a flash memory Software can be altered after the V850E...

Page 476: ...s for 256 KB flash memory versions are shown below 1 Chip erase The area of xx000000H to xx03FFFFH can be erased at the same time 2 Block erase Erasure can be performed in block units 60 KB 4 4 KB 4 Block 0 4 KB Block 1 4 KB Block 2 4 KB Block 3 4 KB Block 4 60 KB Block 5 60 KB Block 6 60 KB Block 7 60 KB ...

Page 477: ...mounting the V850ES SA2 or V850ES SA3 on the target system Remark FA Series is a product of Naito Densei Machida Mfg Co Ltd 18 3 Programming Environment The following shows the environment required for writing programs to the flash memory of V850ES SA2 and V850ES SA3 Figure 18 1 Environment Required for Writing Programs to Flash Memory Host machine RS 232C Dedicated flash programmer V850ES SA2 V85...

Page 478: ...0ES SA3 1 UART0 Transfer rate 4 800 to 76 800 bps Figure 18 2 Communication with Dedicated Flash Programmer UART0 Dedicated flash programmer V850ES SA2 V850ES SA3 VDD VSS RESET TXD0 RXD0 FLMD0 FLMD1 FLMD0 FLMD1 VDD GND RESET RxD TxD 2 CSI0 Serial clock Up to 1 MHz MSB first Figure 18 3 Communication with Dedicated Flash Programmer CSI0 Dedicated flash programmer V850ES SA2 V850ES SA3 FLMD0 FLMD1 V...

Page 479: ...generates the following signals to the V850ES SA2 or V850ES SA3 For details refer to the PG FP4 manual Table 18 1 Signal Generation of Dedicated Flash Programmer PG FP4 PG FP4 V850ES SA2 V850ES SA3 Connection Handling Signal Name I O Pin Function Pin Name CSI0 UART0 CSI0 HS FLMD0 FLMD1 Output Writing enable disable FLMD0 FLMD1 VDD I O VDD voltage generation voltage monitoring VDD GND Ground VSS CL...

Page 480: ...e the output high impedance status 18 5 1 FLMD0 pin In the normal operation mode 0 V is input to the FLMD0 pin In the flash memory programming mode the VDD write voltage is supplied to the FLMD0 pin The following shows an example of the connection of the FLMD0 pin Figure 18 5 FLMD0 Pin Connection Example V850ES SA2 V850ES SA3 FLMD0 Dedicated flash programmer connection pin Pull down resistor RFLMD...

Page 481: ...nals isolate the connection to the other device or set the other device to the output high impedance status Figure 18 6 Conflict of Signals Serial Interface Input Pin V850ES SA2 V850ES SA3 Input pin Conflict of signals Dedicated flash programmer connection pins Other device Output pin In the flash memory programming mode the signal that the dedicated flash programmer sends out conflicts with signa...

Page 482: ...ing so that the input signal to the other device is ignored Figure 18 7 Malfunction of Other Device V850ES SA2 V850ES SA3 Pin Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode if the signal the V850ES SA2 or V850ES SA3 outputs affects the other device isolate the signal on the other device side V850ES SA2 V850ES SA3 Pin Dedicated flash programmer...

Page 483: ... connection pin Reset signal generator Conflict of signals Output pin In the flash memory programming mode the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs Therefore isolate the signals on the reset signal generator side 18 5 4 Port pins including NMI When the flash memory programming mode is set all the port pins except the pins that c...

Page 484: ...ethod 18 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Figure 18 9 Procedure for Manipulating Flash Memory Start Select communication system Manipulate flash memory End Yes Supplies RESET pulse No End Switch to flash memory programming mode ...

Page 485: ...MD1 pins before releasing reset When performing on board writing change modes using a jumper etc Figure 18 10 Flash Memory Programming Mode VDD VDD RESET input FLMD1 input FLMD0 input RXD0 input TXD0 output 0 V VDD 0 V VDD 0 V VDD 0 V VDD 0 V VDD 0 V Note Power ON Oscillation stabilized Communication mode selected Flash control command communication erase write etc Reset cleared Note The number of...

Page 486: ...3 CSI0 HS V850ES SA2 and V850ES SA3 perform slave operation MSB first 8 UART0 Communication rate 9 600 bps at reset LSB first Others RFU Setting prohibited Caution When UART is selected the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse 18 6 4 Communication command The V850ES SA2 and V850ES SA3 communicate with the de...

Page 487: ...es to be written and executes a verify check Verify Verify command Compares the contents of the entire memory and the input data Reset command Escapes from each state Oscillating frequency setting command Sets the oscillation frequency Baud rate setting command Sets the baud rate when using UART Silicon signature command Reads the silicon signature information Version acquisition command Reads the...

Page 488: ...rogramming mode T B D C Storage temperature Tstg 40 to 125 C Note Be sure not to exceed the absolute maximum ratings MAX value of each supply voltage Cautions 1 Do not directly connect the output or I O pins of IC products to each other or to VDD VCC and GND Open drain pins or open collector pins however can be directly connected to each other Direct connection of the output pins between an IC pro...

Page 489: ...0 V Parameter Symbol Conditions MIN TYP MAX Unit Input capacitance CI 10 pF I O capacitance CIO 10 pF Output capacitance CO fX 1 MHz Unmeasured pins returned to 0 V 10 pF Operating conditions VDD AVDD EVDD VDDBU Parameter Symbol Conditions MIN TYP MAX Unit Internal system clock frequency fCLK VDD 2 2 to 2 7 V operation with main clock 0 0625 17 MHz ...

Page 490: ...llation stabilization time Upon STOP mode release Note s Note The TYP value differs depending on the setting of the oscillation stabilization time select register OSTS Caution Ensure that the duty of the oscillation waveform is between 45 and 55 Remarks 1 Connect the oscillator as close as possible to the X1 and X2 pins 2 Do not route the wiring near broken lines 3 For the resonator selection and ...

Page 491: ...fXT 32 32 768 35 kHz Oscillation stabilization time 10 s Caution Ensure that the duty of the oscillation waveform is between 45 and 55 Remarks 1 Connect the oscillator as close as possible to the XT1 and XT2 pins 2 Do not route the wiring near broken lines 3 For the resonator selection and oscillator constant customers are requested to either evaluate the oscillation themselves or apply to the res...

Page 492: ... P40 P42 IOL 3 mA 0 4 V Output voltage low VOL3 Note 5 IOL 1 6 mA 0 4 V Input leakage current high ILIH VIN VDD EVDD VDDBU 5 µA Input leakage current low ILIL VIN 0 V 5 µA Output leakage current high ILOH VO VDD EVDD VDDBU 5 µA Output leakage current low ILOL VO 0 V 5 µA Notes 1 P21 P31 P90 P91 P94 to P97 P99 P911 P914 PCD1 to PCD3 PCM0 to PCM5 PCS0 to PCS7 PCT0 to PCT7 PDH0 to PDH7 PDL0 to PDL15 ...

Page 493: ...ting fXX fCLK 17 MHz T B D T B D mA IDD3 IDLE mode RTC operating fXX fCLK 17 MHz T B D T B D mA Subclock oscillator RTC operating T B D T B D µA IDD4 STOP mode Subclock oscillator stopped XT1 VSS T B D T B D µA IDD5 Subclock operation mode fXT fCLK 32 768 kHz T B D T B D µA IDD6 Sub IDLE mode fXT fCLK 32 768 kHz Main clock oscillator stopped RTC operating T B D T B D µA fXT 32 768 kHz RTC operatin...

Page 494: ...y voltage fall time tFVD1 200 µs Supply voltage hold time from STOP mode setting tHVD1 0 ms STOP release signal input time tDREL1 0 ms Data retention high level input voltage VIHDR1 All input ports VIHn VDDDR1 V Data retention low level input voltage VILDR1 All input ports 0 VILn V Remark n 1 to 5 VDD Setting STOP mode tHVD1 tFVD1 RESET input NMI INTP0 to INTP6 input NMI INTP0 to INTP6 input when ...

Page 495: ...D2 T B D µs Backup supply voltage fall time tFVD2 T B D µs Mode setting time from RESET to VDD tHVD2 T B D ms Mode release signal input time from VDD to RESET tDREL2 T B D ms Caution Shifting to backup mode and restoring from backup mode must be performed at VDD 2 3 V min fCLK 17 MHz and VDD 2 2 V min fCLK 13 5 MHz respectively Setting STOP mode 0 V Note tHVD1 0 8EVDD 0 2EVDD VDD EVDD AVDD VDDBU R...

Page 496: ...VDD VDDBU VDD 0 V VIH VIL VIH VIL Measurement points AC test output measurement points VOH VOL VOH VOL Measurement points Load conditions DUT Device under test CL 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration reduce the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means ...

Page 497: ...TH 12 T 15 ns Data output time from WRm tDWROD 13 15 ns Data output setup time to WRm tSODWR 14 1 n T 20 ns Data output hold time from WRm tHWROD 15 T 15 ns tSAWT1 16 n 1 1 5T 25 ns WAIT setup time to address tSAWT2 17 n 1 1 5 n T 25 ns tHAWT1 18 n 1 0 5 n T ns WAIT hold time from address tHAWT2 19 n 1 1 5 n T ns tSSTWT1 20 n 1 T 25 ns WAIT setup time to ASTB tSSTWT2 21 n 1 1 n T 25 ns tHSTWT1 22 ...

Page 498: ...ST 31 12 7 ns Delay time from CLKOUT to RD WRm tDKRDWR 32 5 14 ns Data input setup time to CLKOUT tSIDK 33 15 ns Data input hold time from CLKOUT tHKID 34 5 ns Data output delay time from CLKOUT tDKOD 35 19 ns WAIT setup time to CLKOUT tSWTK 36 15 ns WAIT hold time from CLKOUT tHKWT 37 5 ns HLDRQ setup time to CLKOUT tSHQK 38 15 ns HLDRQ hold time from CLKOUT tHKHQ 39 5 ns Delay time from CLKOUT t...

Page 499: ...T synchronous asynchronous 1 wait In multiplexed bus mode CLKOUT output A16 to A23 output A0 to A15 output AD0 to AD15 I O ASTB output RD output WAIT input T1 T2 TW T3 29 30 31 1 32 9 8 10 6 20 36 22 21 23 16 18 17 19 37 36 37 5 11 7 31 4 33 34 Address Hi Z 3 32 2 12 Remark WR0 and WR1are high level Data ...

Page 500: ...e CLKOUT synchronous asynchronous 1 wait In multiplexed bus mode CLKOUT output A16 to A23 output A0 to A15 output AD0 to AD15 I O ASTB output WR0 output WR1 output WAIT input T1 T2 TW T3 29 35 31 1 32 9 15 6 20 36 22 21 23 16 18 17 19 37 36 37 14 11 12 2 31 Data Address 13 32 Remark RD is high level ...

Page 501: ...s Manual U15905EJ1V0UD 501 Bus hold In multiplexed bus mode CLKOUT output HLDRQ input HLDAK output A16 to A23 output A0 to A15 output AD0 to AD15 I O ASTB output RD output WR0 output WR1 output 38 39 41 26 25 27 28 38 41 24 TH TH TH TI Hi Z Hi Z Hi Z Data Hi Z 40 ...

Page 502: ... n T 20 ns tHAWT1 54 T ns WAIT hold time from address tHAWT2 55 1 n T ns Remarks 1 T 1 fCPU fCPU CPU operation clock frequency 2 n Number of wait clocks inserted in bus cycle The sampling timing changes when a programmable wait is inserted 3 The values in the above specifications are the values for when clocks with a 1 1 duty ratio are input from X1 b Read cycle CLKOUT synchronous In separate bus ...

Page 503: ...o address tSAWT2 74 1 n T 20 ns tHAWT1 75 T ns WAIT hold time from address tHAWT2 76 1 n T ns Remarks 1 m 0 1 2 T 1 fCPU fCPU CPU operation clock frequency 3 n Number of wait clocks inserted in bus cycle The sampling timing changes when a programmable wait is inserted 4 The values in the above specifications are the values for when clocks with a 1 1 duty ratio are input from X1 d Write cycle CLKOU...

Page 504: ...eliminary User s Manual U15905EJ1V0UD 504 Read cycle CLKOUT asynchronous 1 wait In separate bus mode CLKOUT output T1 47 Hi Z Hi Z 42 44 51 49 50 48 52 54 53 55 46 45 43 TW T2 RD output CS0 to CS3 output A0 to A23 output AD0 to AD15 I O WAIT input ...

Page 505: ...RGET Preliminary User s Manual U15905EJ1V0UD 505 Read cycle CLKOUT synchronous 1 wait In separate bus mode CLKOUT output T1 59 60 61 60 61 56 59 57 58 Hi Z Hi Z TW T2 RD output CS0 to CS3 output A0 to A23 output AD0 to AD15 I O WAIT input 56 ...

Page 506: ...inary User s Manual U15905EJ1V0UD 506 Write cycle CLKOUT asynchronous 1 wait In separate bus mode CLKOUT output T1 68 62 65 64 72 70 71 69 73 75 74 76 67 66 63 TW T2 WR0 WR1 output CS0 to CS3 output A0 to A23 output AD0 to AD15 I O WAIT input Hi Z Hi Z ...

Page 507: ...T Preliminary User s Manual U15905EJ1V0UD 507 Write cycle CLKOUT synchronous 1 wait In separate bus mode CLKOUT output T1 78 79 81 80 79 TW T2 WR0 WR1 output CS0 to CS3 output A0 to A23 output AD0 to AD15 I O WAIT input 77 77 81 80 78 Hi Z Hi Z ...

Page 508: ...itions MIN MAX Unit RESET high level width tWRSH 82 500 ns RESET low level width tWRSL 83 500 ns NMI high level width tWNIH 84 500 ns NMI low level width tWNIL 85 500 ns INTPn high level width tWITH 86 n 0 to 6 analog noise elimination 500 ns INTPn low level width tWITL 87 n 0 to 6 analog noise elimination 500 ns Remark T 1 fXX Reset 82 83 RESET input Interrupt 84 85 NMI input 86 87 INTPn input Re...

Page 509: ...SS VSSBU 0 V CL 50 pF Parameter Symbol Conditions MIN MAX Unit n 0 1 2T 20 ns TIn high level width n 2 to 5 40 ns n 0 1 2T 20 ns TIn low level width n 2 to 5 40 ns TCLRn high level width n 0 1 2T 20 ns TCLRn low level width n 0 1 2T 20 ns INTPnm high level width tWITH nm 00 01 10 11 2T 20 ns INTPnm low level width tWITL nm 00 01 10 11 2T 20 ns Remark T 1 fXX ...

Page 510: ...time from SCKn to SOn output tKSO1 92 30 ns Remark n 0 to 3 V850ES SA2 n 0 to 4 V850ES SA3 2 Slave mode TA 40 to 85 C VDD AVDD EVDD VDDBU 2 2 to 2 7 V VSS AVSS EVSS VSSBU 0 V CL 50 pF Parameter Symbol Conditions MIN MAX Unit SCKn cycle time tKCY2 88 Output 200 ns SCKn high low level width tKH2 tKL2 89 Output 90 ns SIn setup time to SCKn tSIK2 90 50 ns SIn hold time from SCKn tKSI2 91 50 ns Delay t...

Page 511: ...s Stop condition setup time tSU STO 102 4 0 0 6 µs Pulse width with spike suppressed by input filter tSP 103 0 50 ns Capacitance load of each bus line Cb 400 400 pF Notes 1 At the start condition the first clock pulse is generated after the hold time 2 The system requires a minimum of 300 ns hold time internally for the SDA signal at VIHmin of SCL signal in order to occupy the undefined area at th...

Page 512: ...l Conditions MIN TYP MAX Unit Resolution 10 10 10 bit Overall errorNote 1 T B D FSR Conversion time tCONV T B D T B D µs Zero scale errorNote 1 T B D FSR Full scale errorNote 1 T B D FSR Integral linearity errorNote 2 T B D LSB Differential linearity errorNote 2 T B D LSB Analog reference voltage AVREF AVREF0 AVDD 2 2 2 7 V Analog input voltage VIAN AVSS AVREF V AVREF0 current AIREF0 T B D µA AVDD...

Page 513: ... V AVSS VSS 0 V CL 50 pF Parameter Symbol Conditions MIN TYP MAX Unit Resolution 8 8 8 bit Overall errorNote Load conditions 2 MΩ 30 pF AVREF1 VDD T B D FSR Settling time T B D µs Output resistance T B D kΩ Analog reference voltage AVREF AVREF1 VDD 2 2 2 7 V AVREF1 current AVREF1 Per channel T B D mA Note Excludes quantization error 0 05 FSR ...

Page 514: ...Preliminary User s Manual U15905EJ1V0UD 514 CHAPTER 20 PACKAGE DRAWINGS 100 PIN PLASTIC LQFP FINE PITCH 14x14 Package drawing not available resin thickness 1 0 mm 0 5 mm pitch ...

Page 515: ...12x12 ITEM MILLIMETERS D 12 00 0 10 E 12 00 0 10 0 10 P121F1 80 EA6 φ INDEX MARK A w 0 20 A2 A1 A 1 13 e 0 80 1 48 0 10 0 35 0 06 x y 0 20 y1 1 20 ZD 1 20 ZE 0 08 ZE A2 A1 b ZD B A S S w A S w B S y1 S e y 13 12 11 10 9 8 7 6 5 4 3 2 1 N M L K J H G F E D C B A S x A B φ M E D b 0 50 0 05 0 10 ...

Page 516: ...Preliminary User s Manual U15905EJ1V0UD 516 MEMO ...

Page 517: ... 886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 81 44 435 9608 ...

Page 518: ...SNE2 MB95F636KWQN G SNE1 MB95F696KPMC G SNE2 MB95F698KPMC1 G SNE2 MB95F698KPMC2 G SNE2 MB95F698KPMC G SNE2 MB95F818KPMC1 G SNE2 MC908JK1ECDWER MC9S08PA32AVLD MC9S08PT60AVLD R5F1076CMSPV0 R5F5631ECDFBV0 C8051F389 B GQ C8051F392 A GMR ISD ES1600_USB_PROG 901015X SC705C8AE0VFBE STM8TL53G4U6 PIC16F877 04 P B R5F10Y17ASP 30 CY8C3MFIDOCK 125 403708R MB95F354EPF G SNE2 MB95F564KPFT G SNE2 MB95F564KWQN G ...

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