CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
361
(2) Addresses
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected
to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a
unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit data
matches the data values stored in slave address register (SVA). If the 7-bit data matches the SVA register
values, the slave device is selected and communicates with the master device until the master device
transmits a start condition or stop condition.
Figure 12-27. Address
Address
SCL
1
SDA
INTIIC
Note
2
3
4
5
6
7
8
9
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
Note
INTIIC is not generated if data other than a local address or extension code is received during slave
device operation.
The slave address and the eighth bit, which specifies the transfer direction as described in
(3) Transfer
direction specification
below, are written together to the IIC shift register (IIC) and are then output. Received
addresses are written to IIC.
The slave address is assigned to the higher 7 bits of the IIC register.
Summary of Contents for V850ES/SA2 UPD703201
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