CHAPTER 7 TIMER/COUNTER FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
228
(3) Capture operation
The TMn register has two capture/compare registers. These are the CCn0 register and the CCn1 register. A
capture operation or a compare operation is performed according to the settings of both the CMSn1 and
CMSn0 bits of the TMCn1 register. If the CMSn1 and CMSn0 bits of the TMCn1 register are set to 0, the
register operates as a capture register.
A capture operation that captures and holds the TMn count value asynchronously to the count clock is
performed in synchronization with an external trigger. The valid edge that is detected from an external
interrupt request input pin (INTPn0 or INTPn1) is used as an external trigger (capture trigger). The TMn count
value during counting is captured and held in the capture register, in synchronization with that capture trigger
signal. The capture register value is held until the next capture trigger is generated.
Also, an interrupt request (INTCCn0 or INTCCn1) is generated by INTPn0 or INTPn1 signal input.
The valid edge of the capture trigger is set by valid edge select register n (SESn).
If both the rising and falling edges are set as capture triggers, the input pulse width from an external source
can be measured. Also, if only one of the edges is set as the capture trigger, the input pulse cycle can be
measured.
Remark
n = 0, 1
Figure 7-4. Capture Operation Example (TM1)
TM1
0
TMCE1
INTP11
CC11
(Capture register)
n
n
(Capture trigger)
(Capture trigger)
Remarks 1.
When the TMCE1 bit is 0, no capture operation is performed even if INTP11 is input.
2.
Valid edge of INTP11: Rising edge
Summary of Contents for V850ES/SA2 UPD703201
Page 2: ...Preliminary User s Manual U15905EJ1V0UD 2 MEMO ...
Page 285: ... 6 7 ...
Page 516: ...Preliminary User s Manual U15905EJ1V0UD 516 MEMO ...