CHAPTER 9 WATCHDOG TIMER FUNCTIONS
Preliminary User’s Manual U15905EJ1V0UD
277
(3) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operation mode and enables/disables count operations.
This register is a special register that can be written only in a special sequence (refer to
3.4.8 Special
registers
).
The WDTM register is set by an 8-bit or 1-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
RUN
Stops counting
Clears counter and starts counting
RUN
0
1
Selection of watchdog timer operation mode
Note 1
WDTM
0
0
WDTM4
WDTM3
0
0
0
After reset:
00H R/W
Address:
FFFFF6C2H
Interval timer mode
(Upon overflow, maskable interrupt INTWDTM is generated.)
Watchdog timer mode 1
(Upon overflow, non-maskable interrupt INTWDT is generated.)
Watchdog timer mode 2
(Upon overflow, reset operation WDTRES is started.)
WDTM4
0
0
1
1
WDTM3
0
1
0
1
Selection of watchdog timer operation mode
Note 2
< >
Notes 1.
Once the RUN bit is set (to 1), it cannot be cleared (to 0) by software.
Therefore, when counting is started, it cannot be stopped except through RESET input.
2.
Once the WDTM3 and WDTM4 bits are set (to 1), they cannot be cleared (to 0) by software and can
be cleared only through RESET input.
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