CHAPTER 12 SERIAL INTERFACE FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
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IICE
Condition for clearing (IICE = 0)
•
Cleared by instruction
•
When RESET is input
Condition for setting (IICE = 1)
•
Set by instruction
IICE
0
1
Operation stopped. IIC status register (IICS) preset. Internal operation stopped.
Operation enabled.
I
2
C operation enable/disable specification
IICC
LREL
WREL
SPIE
WTIM
ACKE
STT
SPT
After reset:
00H R/W
Address:
FFFFFD82H
Condition for clearing (LREL = 0)
Note
•
Automatically cleared after execution
•
When RESET is input
Condition for setting (LREL = 1)
•
Set by instruction
LREL
0
1
Normal operation
This exits from the current communication operation and sets standby mode. This setting is
automatically cleared after being executed. Its uses include cases in which a locally irrelevant
extension code has been received.
The SCL and SDA lines are set to high impedance.
The following flags are cleared.
•
STD
•
ACKD
•
TRC
•
COI
•
EXC
•
MSTS
•
STT
•
SPT
The standby mode following exit from communications remains in effect until the following communication
entry conditions are met.
•
After a stop condition is detected, restart is in master mode.
•
An address match or extension code reception occurs after the start condition.
Exit from communications
<7>
<6>
Note
This flag’s signal is invalid when IICE = 0.
Remark
STD:
Bit 1 of IIC status register (IICS)
ACKD: Bit 2 of IIC status register (IICS)
TRC:
Bit 3 of IIC status register (IICS)
COI:
Bit 4 of IIC status register (IICS)
EXC:
Bit 5 of IIC status register (IICS)
MSTS: Bit 7 of IIC status register (IICS)
Summary of Contents for V850ES/SA2 UPD703201
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