CHAPTER 4 PORT FUNCTIONS
Preliminary User’s Manual U15905EJ1V0UD
102
(3) Block diagram
Figure 4-3. Block Diagram of P00 and P05
Internal bus
WR
PMC
RD
Address
NMI, INTP4 input
WR
PORT
P00/NMI,
P05/INTP4
PMC0n
WR
INTF
INTF0n
Selector
Selector
WR
PU
PU0n
WR
PM
PM0n
P0n
Noise elimination,
edge detection
WR
INTR
INTR0n
PMC0
INTF0
PU0
PM0
P0
INTR0
EV
DD
P-ch
Remarks 1.
P0:
Port
register
0
PM0: Port mode register 0
PMC0: Port mode control register 0
PU0:
Pull-up resistor option register 0
INTR0: External interrupt rising edge specification register 0
INTF0: External interrupt falling edge specification register 0
2.
n = 0, 5
Summary of Contents for V850ES/SA2 UPD703201
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