CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER)
Preliminary User’s Manual U15905EJ1V0UD
409
13.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3).
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bit 1 is write-only. If
bit 1 is read, the read value is always 0.)
DCHCn
(n = 0 to 3)
DMA transfer had not ended.
DMA transfer had ended.
It is set to 1 when DMA transfer ends and cleared (to 0) when it is read.
TCn
0
1
Status flag indicates whether DMA transfer
through DMA channel n has ended or not
DMA transfer disabled
DMA transfer enabled
This bit is cleared to 0 when DMA transfer ends. It is also cleared to 0 when DMA
transfer is forcibly terminated by means of NMI input.
Enn
0
1
Setting of whether DMA transfer through
DMA channel n is to be enabled or disabled
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn
bit = 1), DMA transfer is started.
STGn
After reset:
00H R/W
Address:
DCHC0: FFFFF0E0H, DCHC1: FFFFF0E2H,
DCHC2: FFFFF0E4H, DCHC3: FFFFF0E6H
TCn
Note 1
0
0
0
0
0
STGn
Enn
Note 2
0
1
2
3
4
5
6
7
Notes 1.
TCn bit is read-only.
2.
STGn bit is write-only.
Caution
Before generating a DMA transfer request by software, make sure that the TCn bit is set to 1
and then clear the TCn bit to 0.
Summary of Contents for V850ES/SA2 UPD703201
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