CHAPTER 7 TIMER/COUNTER FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
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(b) Selection of the internal count clock
TMn operates as a free-running timer.
When the internal clock is specified as the count clock by timer mode control register n1 (TMCn1), TMn is
counted up for each input clock cycle specified by the CSn0 to CSn2 bits of the TMCn0 register (n = 0, 1).
Division by the prescaler can be selected for the count clock from among f
XX
/2, f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32,
f
XX
/64, f
XX
/128, and f
XX
/256 by the TMCn0 register (f
XX
: Internal system clock).
An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an
overflow by setting the OSTn bit of the TMCn1 register to 1.
Caution
The count clock cannot be changed while the timer is operating.
The conditions when the TMn register becomes 0000H are shown below.
(a) Asynchronous reset
•
TMCAEn bit of TMCn0 register = 0
•
Reset input
(b) Synchronous reset
•
TMCEn bit of TMCn0 register = 0
•
The CCn0 register is used as a compare register, and the TMn and CCn0 registers match when clearing
the TMn register is enabled (CCLRn bit of the TMCn1 register = 1)
Summary of Contents for V850ES/SA2 UPD703201
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