www.latticesemi.com
15-1
tn1108_02.5
June 2013
Technical Note TN1108
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The configuration memory in the LatticeECP2™ and LatticeECP2M™ FPGAs is built using volatile SRAM; there-
fore, an external non-volatile configuration memory is required to maintain the configuration data when the power is
removed. This non-volatile memory supplies the configuration data to the LatticeECP2/M when it powers-up, or any
other time the device needs to be updated.
To support multiple configuration options the LatticeECP2/M supports the Lattice sysCONFIG™ interface, as well
as the dedicated ispJTAG™ port. The available configuration options, or ports, are listed in Table 15-1.
Table 15-1. Supported Configuration Ports
This technical note covers all of the configuration options available for LatticeECP2/M.
General Configuration Flow
The LatticeECP2/M will enter configuration mode when one of three things happens, power is applied to the chip,
the PROGRAMN pin is driven low, or when a JTAG Refresh instruction is issued. Upon entering configuration mode
the INITN pin and the DONE pin are driven low to indicate that the device is initializing, i.e. getting ready to receive
configuration data.
Once the LatticeECP2/M has finished initializing, the INITN pin will be driven high. The low to high transition of the
INITN pin causes the CFG pins to be sampled, telling the LatticeECP2/M which port it is going to configure from.
The LatticeECP2/M then begins reading data from the selected port and starts looking for the preamble, BDB3
(hex). All data after the preamble is valid configuration data.
When the LatticeECP2/M has finished reading all of the configuration data, assuming there have been no errors,
the DONE pin goes high and the LatticeECP2/M enters user mode, in other words the device begins to function
according to the user’s design.
Note that the LatticeECP2/M may also be programmed via JTAG. When programming via JTAG, the INITN and
DONE signals have no meaning, because JTAG, per the IEEE standard, takes complete control of the chip and it’s
I/Os.
The Lattice ECP2/M devices are also available in an "S" version which supports the use of an encrypted bitstream
configuration file. These versions have the same configuration options as the standard versions, except where
noted in this document. When using these devices, the user should refer to the
LatticeECP2/M Family Data Sheet
and TN1109,
LatticeECP2/M Configuration Encryption Usage Guide
, in addition to this document, to understand
the configuration requirements.
The following sections define each configuration pin, each configuration mode, and all of the configuration options
for the LatticeECP2/M.
Interface
Port
sysCONFIG
SPI
SPIm
Slave Serial
Slave Parallel
ispJTAG
JTAG (IEEE 1149.1 and IEEE 1532 compliant)
LatticeECP2/M sysCONFIG
Usage Guide
