CHAPTER 6 CLOCK GENERATION FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
209
Examples of settings to change between the main clock and subclock are shown below
(a) Example of setting when changing from main clock to subclock
<1> Checking internal system clock: Check if the following condition is satisfied.
•
Internal system clock (f
XX
) > Subclock (32.768 kHz)
×
4
If this condition is not satisfied, change the setting of the CK2, CK1,
and CK0 bits so that the condition is satisfied. At this time, do not
change the setting of the CK3 bit.
<2> CK3 bit
←
“1”:
Use of a bit manipulation instruction is recommended. Do not
change the setting of the CK2, CK1, and CK0 bits.
<3> Subclock operation:
The following time is required between when the CK3 bit is set and
when the subclock operation is started:
•
Maximum: (1/Subclock frequency)
Therefore, read the CLS bit and confirm that the subclock operation
has started.
<4> MCK
←
“0”:
Clear MCK to 0 only when stopping the main clock.
(b) Example of setting when changing subclock to main clock
<1> MCK
←
“1”:
Oscillation of the main clock is started.
<2> Software wait:
Insert wait states by program and wait until the oscillation stabilization time of
the main clock elapses.
<3> CK3
←
“0”:
Use of a bit manipulation instruction is recommended. Do not change the
setting of the CK2, CK1, and CK0 bits.
<3> Main clock operation: The following time is required between when the CK3 bit is set and when the
main clock specified by the CK2, CK1, and CK0 bits is selected.
•
Maximum: (1/Subclock frequency)
Therefore, read the CLS bit and confirm that the main clock operation has
started.
Summary of Contents for V850ES/SA2 UPD703201
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