CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Preliminary User’s Manual U15905EJ1V0UD
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14.3.2 Restore
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
of the restored PC.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit
of the PSW is 0.
<2> Transfers control to the address of the restored PC and PSW.
Figure 14-5 illustrates the processing of the RETI instruction.
Figure 14-5. RETI Instruction Processing
PSW.EP
RETI instruction
PSW.NP
Restores original processing
1
1
0
0
PC
PSW
Corresponding
bit of ISPR
Note
EIPC
EIPSW
0
PC
PSW
FEPC
FEPSW
Note
For the ISPR register, see
14.3.6 In-service priority register (ISPR)
.
Caution
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by
the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the
LDSR instruction immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
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