NEC V850E/MS1 UPD703100, User Manual

Page: 192 / 449

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U12688EJ4V0UM00
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6.11 Interrupting DMA Transfer
6.11.1 Interruption factors
DMA transfer is interrupted if the following factors occur.
•
Bus hold
•
Refresh cycle
If the factor that is interrupting DMA transfer disappears, DMA transfer promptly restarts.
6.11.2 Forcible interruption
DMA transfer can be forcibly interrupted by an NMI input during DMA transfer.
At such a time, the DMAC resets the ENn bit of the DCHCn register of all channels (0) and activates the DMA
transfer disabled state, after which the DMA transfer being executed when the NMI was input is terminated (n = 0 to
3).
When in the single step mode or block transfer mode, the DMA transfer request is held in the DMAC. If the ENn
bit is reset (1), DMA transfer restarts from the point where it was interrupted.
When in the single transfer mode, if the ENn bit is set (1), the next DMA transfer request is received and DMA
transfer starts.
6.12 Terminating DMA Transfer
6.12.1 DMA transfer end interrupt
When DMA transfer ends and the TC bit of the corresponding DCHCn register is set (1), a DMA transfer end
interrupt (INTDMAn) is issued (n = 0 to 3) to the interrupt controller (INTC).
6.12.2 Terminal count output
In the TI state directly after the cycle when DMA transfer ends (TE state), the TCn signal output becomes active
for 1 clock cycle.