NEC V850E/MS1 UPD703100, User Manual

Page: 233 / 449

CHAPTER 8 CLOCK GENERATOR FUNCTIONS
User’s Manual U12688EJ4V0UM00
233
8.3.3 Clock control register (CKC)
When in the PLL mode, this is an 8-bit register which controls the internal system clock frequency (
φ
), and it can
be written to only by a specific combination of instruction sequences so that it cannot be rewritten easily by mistake
due to program runaway.
This register can be read/written in 8- or 1-bit units.
Caution When in the direct mode, do not change the setting of this register.
Address
FFFFF072H
7
0 CKC
6
0
5
0
4
0
3
0
2
0
1
CKDIV1
0
CKDIV0
After reset
00H
Bit Position Bit Name Function
Clock Divide
Sets the internal system clock frequency (
φ
) when in the PLL mode.
CKDIV1 CKDIV0 Internal System Clock (
φ
)
0 0 5
×
f
XX
0 1 Setting prohibited
1 0 f
XX
1 1 f
XX
/2
1, 0 CKDIV1,
CKDIV0
The sequence of setting data to this register is the same as for the power save control register (PSC). However,
the restrictions shown in Remark 2 of 3.4.9 Specific registers do not apply. For details, refer to 8.5.2 Control
registers.
Example Clock generator setting
CKC Register Operation
Mode
CKSEL Pin
CKDIV1 Bit CKDIV0 Bit
Input Clock
(f
XX
)
Internal System
Clock (
φ
)
Direct mode High-level input 0 0 16 MHz 8 MHz
0 0 8 MHz 40 MHz
1 0 8 MHz 8 MHz
PLL mode Low-level input
1 1 8 MHz 4 MHz
Other than above Setting prohibited