NEC V850E/MS1 UPD703100, User Manual

Page: 232 / 449

CHAPTER 8 CLOCK GENERATOR FUNCTIONS
User’s Manual U12688EJ4V0UM00
232
8.3 Input Clock Selection
The clock generator is configured from an oscillator and a PLL synthesizer. If, for example an 8 MHz crystal
resonator or ceramic resonator is connected to pins X1 and X2, an internal system clock (
φ
) of 40 MHz can be
generated.
Also, an external clock can be input directly to the oscillator. In this case, input a clock signal to the X1 pin only
and leave the X2 pin open.
Two types of mode, a PLL mode and a direct mode, are provided as the basic operation modes for the clock
generator. Selection of the operation mode is done by the CKSEL pin. The input of this pin latches at reset time.
CKSEL Operation Mode
0 PLL mode
1 Direct mode
Caution Fix the input level of the CKSEL pin before use. If it is switched during operation, there is a
possibility of malfunction occurring.
8.3.1 Direct mode
In the direct mode, an external clock with double the internal system clock’s frequency is input. Since the
oscillator and PLL synthesizer are not operating, a large amount of power can be saved. Mainly, the V850E/MS1 is
used in application systems where it operates at relatively low frequencies. In consideration of EMI
countermeasures, if the external clock frequency (f
XX
) is 32 MHz (internal system clock (
φ
) = 16 MHz) or greater, the
PLL mode is recommended.
Caution In the direct mode, be sure to input an external clock (do not connect an external resonator).
8.3.2 PLL mode
In the PLL mode, by connecting an external resonator or inputting an external clock and multiplying this clock by
the PLL synthesizer, an internal system clock (
φ
) is generated.
At reset time, an internal system clock (
φ
) which is 5 times the frequency of the input clock’s frequency (f
XX
) (5
×
f
XX
), is generated.
In the PLL mode, if the clock supply from an external resonator or external clock source stops, the internal system
clock (
φ
) continues to operate based on the self-propelled frequency of the clock generator’s internal voltage
controlled oscillator (VCO). In this case,
φ
= approx. 1 MHz (target). However, do not devise an application method
in which you expect to use this self-propelled frequency.
Example Clock used when in the PLL mode
System Clock Frequency (
φ
) [MHz] External Resonator/External Clock Frequency (f
XX
) [MHz]
40.000 8.0000
32.768 6.5536
25.000 5.0000
20.000 4.0000
16.384 3.2768