CHAPTER 11 A/D CONVERTER
User’s Manual U12688EJ4V0UM00
319
Note In the timer trigger mode (4-trigger mode) during the scan mode, because the scanning sequence of the
ANI0 to ANI3 pins is specified by the sequence in which the match signals are generated from the
compare register, the number of trigger inputs should be specified instead of a certain analog input pin.
When ANIS2 is set to 1, the scan mode shifts to A/D trigger mode after counting the trigger four times,
and then starts converting.
Cautions 1.
When the CE bit is 1 in the timer trigger mode and external trigger mode, the trigger
signal standby state is set. To clear the CE bit, write 0 or reset.
In the A/D trigger mode, the conversion trigger is set by writing 1 to the CE bit. After the
operation, when the mode is changed to the timer trigger mode or external trigger mode
without clearing the CE bit, the trigger input standby state is set immediately after the
change.
2.
It takes 3 clocks for CS bit to become 1 after A/D conversion starts.
Summary of Contents for V850E/MS1 UPD703100
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