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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U12688EJ4V0UM00
229
7.7
Interrupt Latency Time
The following table describes the V850E/MS1 interrupt latency time (from interrupt generation to start of interrupt
processing).
Figure 7-13. Pipeline Operation at Interrupt Request Acknowledgement (Outline)
IF
ID
EX
2 system
clocks
4 system
clocks
CLKOUT
Instruction 1
Instruction 2
Interrupt acknowledgement operation
Instruction (start instruction of
interrupt processing routine)
Interrupt request
IF
ID
EX MEM WB
IF
×
ID
×
INT1 INT2 INT3 INT4
Remark
INT1 to INT4: Interrupt acknowledgement processing
IF
×
:
Invalid instruction fetch
ID
×
:
Invalid instruction decode
Interrupt Latency Time (Internal System Clock)
Internal interrupt
External interrupt
Condition
Minimum
5
7
Maximum
11
13
The following cases are exceptions.
•
In IDLE/software STOP mode
•
External bus is accessed
•
Two or more interrupt request non-sample instructions
are executed in succession
•
Access to interrupt control register
7.8
Periods in Which Interrupt Is Not Acknowledged
An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged
between an interrupt non-sample instruction and the next instruction.
The interrupt request non-sampling instructions are as follows.
•
EI instruction
•
DI instruction
•
LDSR reg2, 0x5 instruction (vs. PSW)
•
The store instruction for the interrupt control register (xxlCn) and command register (PRCMD)
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